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nand flash memory MT29F4G08ABADAH4, mt29f4g08abadawp, mt29f4g08abbdah4, mt29f4g08abbdahc, mt29f4g16abadah4, mt29f4g16abadawp, mt29f4g16abbdah4, mt29f4g16abbdahc, mt29f8g08adadah4, mt29f8g08adbdah4, mt29f8g16adadah4, mt29f8g16adbdah4, mt29f16g08ajadawp features ? open nand flash interface (onfi) 1.0-compliant 1 ? single-level cell (slc) technology ? organization C page size x8: 2112 bytes (2048 + 64 bytes) C page size x16: 1056 words (1024 + 32 words) C block size: 64 pages (128k + 4k bytes) C plane size: 2 planes x 2048 blocks per plane C device size: 4gb: 4096 blocks; 8gb: 8192 blocks 16gb: 16,384 blocks ? asynchronous i/o performance C t rc/ t wc: 20ns (3.3v), 25ns (1.8v) ? array performance C read page: 25s 3 C program page: 200s (typ: 1.8v, 3.3v) 3 C erase block: 700s (typ) ? command set: onfi nand flash protocol ? advanced command set C program page cache mode 4 C read page cache mode 4 C one-time programmable (otp) mode C two-plane commands 4 C interleaved die (lun) operations C read unique id C block lock (1.8v only) C internal data move ? operation status byte provides software method for detecting C operation completion C pass/fail condition C write-protect status ? ready/busy# (r/b#) signal provides a hardware method of detecting operation completion ? wp# signal: write protect entire device ? first block (block address 00h) is valid when ship- ped from factory with ecc. for minimum required ecc, see error management. ? block 0 requires 1-bit ecc if program/erase cy- cles are less than 1000 ? reset (ffh) required as first command after pow- er-on ? alternate method of device initialization (nand_in- it) after power up (contact factory) ? internal data move operations supported within the plane from which data is read ? quality and reliability C data retention: 10 years C endurance: 100,000 program/erase cycles ? operating voltage range C v cc : 2.7C3.6v C v cc : 1.7C1.95v ? operating temperature: C commercial: 0c to +70c C industrial (it): C40oc to +85oc ? package C 48-pin tsop type 1, cpl 2 C 63-ball vfbga notes: 1. the onfi 1.0 specification is available at www.onfi.org . 2. cpl = center parting line. 3. see program and erase characteristics for t r_ecc and t prog_ecc specifications. 4. these commands supported only with ecc disabled. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
part numbering information micron nand flash devices are available in different configurations and densities. verify valid part numbers by using microns part catalog search at www.micron.com . to compare features and specifications by device type, visit www.micron.com/products . contact the factory for devices not found. figure 1: marketing part number chart mt 29f 4g 08 a b a d a wp it es :d micron technology product family 29f = nand flash memory density 4g = 4gb 8g = 8gb 16g = 16gb device width 08 = 8-bit 16 = 16-bit level a = slc classification mark die nce rnb i/o channels b 1 1 1 1 d 2 1 1 1 operating voltage range a = 3.3v (2.7C3.6v) b = 1.8v (1.7C1.95v) feature set d = feature set d design revision (shrink) production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample special options blank x = product longevity program (plp) operating temperature range blank = commercial (0c to +70c) it = industrial (C40c to +85c) speed grade blank package code wp = 48-pin tsop 1 hc = 63-ball vfbga (10.5 x 13 x 1.0mm) h4 = 63-ball vfbga (9 x 11 x 1.0mm) interface a = async only j 4 2 1 2 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 8 signal descriptions ........................................................................................................................................... 8 signal assignments ........................................................................................................................................... 9 package dimensions ....................................................................................................................................... 12 architecture ................................................................................................................................................... 15 device and array organization ........................................................................................................................ 16 asynchronous interface bus operation ........................................................................................................... 20 asynchronous enable/standby ................................................................................................................... 20 asynchronous commands .......................................................................................................................... 20 asynchronous addresses ............................................................................................................................ 22 asynchronous data input ........................................................................................................................... 23 asynchronous data output ......................................................................................................................... 24 write protect# ............................................................................................................................................ 25 ready/busy# .............................................................................................................................................. 25 device initialization ....................................................................................................................................... 30 command definitions .................................................................................................................................... 31 reset operations ............................................................................................................................................ 34 reset (ffh) ............................................................................................................................................... 34 identification operations ................................................................................................................................ 35 read id (90h) ............................................................................................................................................ 35 read id parameter tables .............................................................................................................................. 36 read parameter page (ech) ...................................................................................................................... 39 parameter page data structure tables ............................................................................................................. 40 bare die parameter page data structure tables ................................................................................................ 45 read unique id (edh) ................................................................................................................................ 48 feature operations ......................................................................................................................................... 49 set features (efh) .................................................................................................................................. 50 get features (eeh) ................................................................................................................................. 51 status operations ........................................................................................................................................... 54 read status (70h) ................................................................................................................................... 55 read status enhanced (78h) ................................................................................................................ 55 column address operations ........................................................................................................................... 57 random data read (05h-e0h) ................................................................................................................ 57 random data read two-plane (06h-e0h) ............................................................................................ 58 random data input (85h) ...................................................................................................................... 59 program for internal data input (85h) ........................................................................................... 60 read operations ............................................................................................................................................. 62 read mode (00h) ..................................................................................................................................... 64 read page (00h-30h) ................................................................................................................................ 64 read page cache sequential (31h) ...................................................................................................... 65 read page cache random (00h-31h) .................................................................................................... 66 read page cache last (3fh) .................................................................................................................. 68 read page two-plane 00h-00h-30h ....................................................................................................... 69 program operations ....................................................................................................................................... 71 program page (80h-10h) ......................................................................................................................... 72 program page cache (80h-15h) ............................................................................................................. 72 program page two-plane (80h-11h) .................................................................................................... 75 erase operations ............................................................................................................................................ 77 erase block (60h-d0h) ............................................................................................................................ 77 erase block two-plane (60h-d1h) ....................................................................................................... 78 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
internal data move operations ....................................................................................................................... 79 read for internal data move (00h-35h) ............................................................................................. 80 program for internal data move (85hC10h) ..................................................................................... 81 program for internal data move two-plane (85h-11h) ................................................................. 82 block lock feature ......................................................................................................................................... 83 wp# and block lock ................................................................................................................................... 83 unlock (23h-24h) .................................................................................................................................... 83 lock (2ah) ................................................................................................................................................ 86 lock tight (2ch) ..................................................................................................................................... 87 block lock read status (7ah) .............................................................................................................. 88 one-time programmable (otp) operations .................................................................................................... 90 legacy otp commands .............................................................................................................................. 90 otp data program (80h-10h) ................................................................................................................. 91 random data input (85h) ...................................................................................................................... 92 otp data protect (80h-10) ..................................................................................................................... 93 otp data read (00h-30h) ......................................................................................................................... 95 two-plane operations .................................................................................................................................... 97 two-plane addressing ................................................................................................................................ 97 interleaved die (multi-lun) operations ......................................................................................................... 106 error management ........................................................................................................................................ 107 internal ecc and spare area mapping for ecc ............................................................................................... 109 electrical specifications ................................................................................................................................. 111 electrical specifications C dc characteristics and operating conditions .......................................................... 113 electrical specifications C ac characteristics and operating conditions .......................................................... 115 electrical specifications C program/erase characteristics ................................................................................ 118 asynchronous interface timing diagrams ...................................................................................................... 119 revision history ............................................................................................................................................ 131 rev. n C 10/12 ............................................................................................................................................ 131 rev. m C 02/12 ........................................................................................................................................... 131 rev. l C 1/12 .............................................................................................................................................. 131 rev. k C 11/11 ............................................................................................................................................ 131 rev. j C 09/11 ............................................................................................................................................. 131 rev. i C 07/11 ............................................................................................................................................. 131 rev. h C 12/10 ............................................................................................................................................ 131 rev. g C 10/10 ............................................................................................................................................ 131 rev. f C 06/10 ............................................................................................................................................ 131 rev. e C 05/10 ............................................................................................................................................ 131 rev. d C 03/10 ............................................................................................................................................ 132 rev. c C 01/10 ............................................................................................................................................ 132 rev. b C 10/09 ............................................................................................................................................ 132 rev. a C 07/09 ............................................................................................................................................ 132 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
list of tables table 1: signal definitions ............................................................................................................................... 8 table 2: array addressing C mt29f4g08 (x8) .................................................................................................. 16 table 3: array addressing C mt29f4g16 (x16) ................................................................................................. 17 table 4: array addressing C mt29f8g08 and mt29f16g08 (x8) ....................................................................... 18 table 5: array addressing C mt29f8g16 ( x16) ................................................................................................ 19 table 6: asynchronous interface mode selection ............................................................................................ 20 table 7: command set .................................................................................................................................. 31 table 8: two-plane command set .................................................................................................................. 33 table 9: read id parameters for address 00h ................................................................................................. 36 table 10: read id parameters for address 20h ............................................................................................... 38 table 11: parameter page data structure ........................................................................................................ 40 table 12: parameter page data structure ........................................................................................................ 45 table 13: feature address definitions ............................................................................................................. 49 table 14: feature address 90h C array operation mode ................................................................................... 50 table 15: feature addresses 01h: timing mode ............................................................................................... 52 table 16: feature addresses 80h: programmable i/o drive strength ................................................................ 53 table 17: feature addresses 81h: programmable r/b# pull-down strength ...................................................... 53 table 18: status register definition ................................................................................................................ 54 table 19: block lock address cycle assignments ............................................................................................ 85 table 20: block lock status register bit definitions ........................................................................................ 88 table 21: error management details ............................................................................................................. 107 table 22: absolute maximum ratings ............................................................................................................ 111 table 23: recommended operating conditions ............................................................................................. 111 table 24: valid blocks ................................................................................................................................... 111 table 25: capacitance ................................................................................................................................... 112 table 26: test conditions .............................................................................................................................. 112 table 27: dc characteristics and operating conditions (3.3v) ....................................................................... 113 table 28: dc characteristics and operating conditions (1.8v) ....................................................................... 114 table 29: ac characteristics: command, data, and address input (3.3v) ........................................................ 115 table 30: ac characteristics: command, data, and address input (1.8v) ........................................................ 115 table 31: ac characteristics: normal operation (3.3v) .................................................................................. 116 table 32: ac characteristics: normal operation (1.8v) .................................................................................. 116 table 33: program/erase characteristics ....................................................................................................... 118 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
list of figures figure 1: marketing part number chart ............................................................................................................ 2 figure 2: 48-pin tsop C type 1 (top view) ........................................................................................................ 9 figure 3: 63-ball vfbga, x8 (balls down, top view) ........................................................................................ 10 figure 4: 63-ball vfbga, x16 (balls down, top view) ...................................................................................... 11 figure 5: 48-pin tsop C type 1, cpl ............................................................................................................... 12 figure 6: 63-ball vfbga (10.5mm x 13mm) .................................................................................................... 13 figure 7: 63-ball vfbga (9mm x 11mm) ......................................................................................................... 14 figure 8: nand flash die (lun) functional block diagram ............................................................................ 15 figure 9: array organization C mt29f4g08 (x8) .............................................................................................. 16 figure 10: array organization C mt29f4g16 (x16) .......................................................................................... 17 figure 11: array organization C mt29f8g08 and mt29f16g08 (x8) ................................................................. 18 figure 12: array organization C mt29f8g16 (x16) .......................................................................................... 19 figure 13: asynchronous command latch cycle ............................................................................................ 21 figure 14: asynchronous address latch cycle ................................................................................................ 22 figure 15: asynchronous data input cycles .................................................................................................... 23 figure 16: asynchronous data output cycles ................................................................................................. 24 figure 17: asynchronous data output cycles (edo mode) ............................................................................. 25 figure 18: read/busy# open drain .............................................................................................................. 26 figure 19: t fall and t rise (3.3v v cc ) ................................................................................................................ 27 figure 20: t fall and t rise (1.8v v cc ) ................................................................................................................ 27 figure 21: i ol vs. rp (v cc = 3.3v v cc ) .............................................................................................................. 28 figure 22: i ol vs. rp (1.8v v cc ) ....................................................................................................................... 28 figure 23: tc vs. rp ....................................................................................................................................... 29 figure 24: r/b# power-on behavior ............................................................................................................... 30 figure 25: reset (ffh) operation .................................................................................................................. 34 figure 26: read id (90h) with 00h address operation .................................................................................... 35 figure 27: read id (90h) with 20h address operation .................................................................................... 35 figure 28: read parameter (ech) operation .............................................................................................. 39 figure 29: read unique id (edh) operation ............................................................................................... 48 figure 30: set features (efh) operation .................................................................................................... 50 figure 31: get features (eeh) operation .................................................................................................... 51 figure 32: read status (70h) operation ...................................................................................................... 55 figure 33: read status enhanced (78h) operation ................................................................................... 56 figure 34: random data read (05h-e0h) operation ................................................................................... 57 figure 35: random data read two-plane (06h-e0h) operation .............................................................. 58 figure 36: random data input (85h) operation ........................................................................................ 59 figure 37: program for internal data input (85h) operation .............................................................. 61 figure 38: read page (00h-30h) operation ................................................................................................... 65 figure 39: read page (00h-30h) operation with internal ecc enabled .......................................................... 65 figure 40: read page cache sequential (31h) operation ......................................................................... 66 figure 41: read page cache random (00h-31h) operation ....................................................................... 67 figure 42: read page cache last (3fh) operation ..................................................................................... 68 figure 43: read page two-plane (00h-00h-30h) operation ........................................................................ 70 figure 44: program page (80h-10h) operation ............................................................................................ 72 figure 45: program page cache (80hC15h) operation (start) ..................................................................... 74 figure 46: program page cache (80hC15h) operation (end) ...................................................................... 74 figure 47: program page two-plane (80hC11h) operation ....................................................................... 76 figure 48: erase block (60h-d0h) operation .............................................................................................. 77 figure 49: erase block two-plane (60hCd1h) operation .......................................................................... 78 figure 50: read for internal data move (00h-35h) operation ................................................................ 80 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 51: read for internal data move (00hC35h) with random data read (05hCe0h) ..................... 80 figure 52: internal data move (85h-10h) with internal ecc enabled ........................................................ 81 figure 53: internal data move (85h-10h) with random data input with internal ecc enabled ............ 81 figure 54: program for internal data move (85hC10h) operation ........................................................ 81 figure 55: program for internal data move (85h-10h) with random data input (85h) .................... 82 figure 56: program for internal data move two-plane (85h-11h) operation .................................... 82 figure 57: flash array protected: invert area bit = 0 ........................................................................................ 84 figure 58: flash array protected: invert area bit = 1 ........................................................................................ 84 figure 59: unlock operation ....................................................................................................................... 85 figure 60: lock operation ............................................................................................................................ 86 figure 61: lock tight operation ................................................................................................................. 87 figure 62: program/erase issued to locked block ...................................................................................... 88 figure 63: block lock read status .......................................................................................................... 88 figure 64: block lock flowchart ................................................................................................................ 89 figure 65: otp data program (after entering otp operation mode) ........................................................... 92 figure 66: otp data program operation with random data input (after entering otp operation mode) ... 93 figure 67: otp data protect operation (after entering otp protect mode) ................................................. 94 figure 68: otp data read ........................................................................................................................... 95 figure 69: otp data read with random data read operation ................................................................. 96 figure 70: two-plane page read .............................................................................................................. 98 figure 71: two-plane page read with random data read .................................................................... 99 figure 72: two-plane program page ....................................................................................................... 99 figure 73: two-plane program page with random data input .......................................................... 100 figure 74: two-plane program page cache mode ............................................................................... 101 figure 75: two-plane internal data move ........................................................................................... 102 figure 76: two-plane internal data move with two-plane random data read ............................ 103 figure 77: two-plane internal data move with random data input ............................................... 104 figure 78: two-plane block erase ......................................................................................................... 105 figure 79: two-plane/multiple-die read status cycle ........................................................................ 105 figure 80: spare area mapping (x8) ............................................................................................................... 109 figure 81: spare area mapping (x16) ............................................................................................................. 110 figure 82: reset operation .......................................................................................................................... 119 figure 83: read status cycle ..................................................................................................................... 119 figure 84: read status enhanced cycle .................................................................................................. 120 figure 85: read parameter page ............................................................................................................. 120 figure 86: read page .................................................................................................................................. 121 figure 87: read page operation with ce# dont care ............................................................................... 122 figure 88: random data read .................................................................................................................. 123 figure 89: read page cache sequential ................................................................................................ 124 figure 90: read page cache random ...................................................................................................... 125 figure 91: read id operation ...................................................................................................................... 126 figure 92: program page operation .......................................................................................................... 126 figure 93: program page operation with ce# dont care ........................................................................ 127 figure 94: program page operation with random data input .............................................................. 127 figure 95: program page cache .............................................................................................................. 128 figure 96: program page cache ending on 15h ........................................................................................ 128 figure 97: internal data move ............................................................................................................... 129 figure 98: internal data move (85h-10h) with internal ecc enabled ....................................................... 129 figure 99: internal data move (85h-10h) with random data input with internal ecc enabled ................. 130 figure 100: erase block operation ............................................................................................................ 130 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory features pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description micron nand flash devices include an asynchronous data interface for high-perform- ance i/o operations. these devices use a highly multiplexed 8-bit bus (i/ox) to transfer commands, address, and data. there are five control signals used to implement the asynchronous data interface: ce#, cle, ale, we#, and re#. additional signals control hardware write protection and monitor device status (r/b#). this hardware interface creates a low pin-count device with a standard pinout that re- mains the same from one density to another, enabling future upgrades to higher densi- ties with no board redesign. a target is the unit of memory accessed by a chip enable signal. a target contains one or more nand flash die. a nand flash die is the minimum unit that can independently execute commands and report status. a nand flash die, in the onfi specification, is referred to as a logical unit (lun). there is at least one nand flash die per chip enable signal. for further details, see device and array organization. this device has an internal 4-bit ecc that can be enabled using the get/set features. see internal ecc and spare area mapping for ecc for more information. signal descriptions table 1: signal definitions signal 1 type description 2 ale input address latch enable: loads an address from i/o[7:0] into the address register. ce# ce#2 input chip enable: enables or disables one or more die (luns) in a target. for the 16gb device, ce# controls the first 8gb of memory; ce2# controls the second 8gb of memory. cle input command latch enable: loads a command from i/o[7:0] into the command register. lock input when lock is high during power-up, the block lock function is enabled. to disable the block lock, connect lock to v ss during power-up, or leave it disconnected (internal pull-down). re# input read enable: transfers serial data from the nand flash to the host system. we# input write enable: transfers commands, addresses, and serial data from the host system to the nand flash. wp# input write protect: enables or disables array program and erase operations. i/o[7:0] (x8) i/o[15:0] (x16) i/o data inputs/outputs: the bidirectional i/os transfer address, data, and command infor- mation. r/b# r/b#2 output ready/busy: an open-drain, active-low output that requires an external pull-up resistor. this signal indicates target array activity. for the 16gb device, r/b# indicates the status of the first 8gb of memory; r/b# indicates the status of the second 8gb of memory. v cc supply v cc : core power supply v ss supply v ss : core ground connection nc C no connect: ncs are not internally connected. they can be driven or left unconnected. dnu C do not use: dnus must be left unconnected. notes: 1. see device and array organization for detailed signal connections. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory general description pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
2. see asynchronous interface bus operation for detailed asynchronous interface signal descriptions. signal assignments figure 2: 48-pin tsop C type 1 (top view) x8 nc nc nc nc nc r/b2# 3 r/b# re# ce# ce2# 3 nc v cc v ss nc nc cle ale we# wp# nc nc nc nc nc x16 nc nc nc nc nc r/b#2 3 r/b# re# ce# ce2# 3 nc v cc v ss nc nc cle ale we# wp# nc nc nc nc nc x8 v ss 1 dnu nc nc i/o7 i/o6 i/o5 i/o4 nc v cc 1 dnu 2 v cc v ss nc v cc 1 nc i/o3 i/o2 i/o1 i/o0 nc nc dnu v ss 1 x16 v ss i/o15 i/o14 i/o13 i/o7 i/o6 i/o5 i/o4 i/o12 v cc dnu 2 v cc v ss nc v cc i/o11 i/o3 i/o2 i/o1 i/o0 i/o10 i/o9 i/o8 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 notes: 1. these pins might not be bonded in the package; however, micron recommends that the customer connect these pins to the designated external sources for onfi compatibility. 2. for the 3v device, pin 38 is dnu. for the 1.8v device, pin 38 is lock. 3. r/b2# and ce2# are available on 16gb devices only. they are nc for other configura- tions. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory signal assignments pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 3: 63-ball vfbga, x8 (balls down, top view) 3 wp# vcc 2 nc nc dnu nc nc vss 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc 8 r/b# nc nc nc dnu vcc i/o7 vss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc lock 1 nc nc i/o3 7 we# nc nc vss 2 nc nc i/o5 i/o6 6 ce# nc nc nc nc nc vcc i/o4 4 ale re# nc nc vcc 2 i/o0 i/o1 i/o2 notes: 1. for the 3v device, g5 changes to dnu. no lock function is available on the 3.3v de- vice. 2. these pins might not be bonded in the package; however, micron recommends that the customer connect these pins to the designated external sources for onfi compatibility. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory signal assignments pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 4: 63-ball vfbga, x16 (balls down, top view) 3 wp# vcc nc nc dnu i/o8 i/o9 vss 4 ale re# nc nc vcc i/o0 i/o1 i/o2 8 r/b# nc nc nc dnu vcc i/o7 vss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc lock 1 i/o10 i/o11 i/o3 7 we# nc nc vss i/o15 i/o14 i/o5 i/o6 6 ce# nc nc nc i/o13 i/o12 vcc i/o4 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc note: 1. for the 3v device, g5 changes to dnu. no lock function is available on the 3.3v de- vice. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory signal assignments pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
package dimensions figure 5: 48-pin tsop C type 1, cpl 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. note: 1. all dimensions are in millimeters. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory package dimensions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 6: 63-ball vfbga (10.5mm x 13mm) ball a1 id 1.0 max 13 0.1 ball a1 id 0.8 typ 10.5 0.1 0.65 0.05 seating plane a 8.8 ctr 7.2 ctr 0.12 a 63x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post- reflow on ?0.4 smd ball pads. 0.25 min 0.8 typ 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m bottom side saw fiducials may or may not be covered with soldermask. note: 1. all dimensions are in millimeters. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory package dimensions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 7: 63-ball vfbga (9mm x 11mm) ball a1 id seating plane 0.1 a a 1.0 max 0.25 min 9 0.1 ball a1 id (covered by sr) 8.8 ctr dimensions apply to solder balls post- reflow on ?0.4 smd ball pads. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). a b c d e f g h j k l m 10 9 8 7 6 5 4 3 2 1 63x ?0.45 11 0.1 0.8 typ 0.8 typ 7.2 ctr note: 1. all dimensions are in millimeters. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory package dimensions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control de- vice operations. the addresses are latched by an address register and sent to a row de- coder to select a row address, or to a column decoder to select a column address. data is transferred to or from the nand flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. the nand flash memory array is programmed and read using page-based operations and is erased using block-based operations. during normal page operations, the data and cache registers act as a single register. during cache operations, the data and cache registers operate independently to increase data throughput. the status register reports the status of die operations. figure 8: nand flash die (lun) functional block diagram address register data register cache register ecc status register command register ce# v cc v ss cle ale we# re# wp# lock 1 i/ox control logic i/o control r/b# row decode column decode nand flash array (2 planes) note: 1. the lock pin is used on the 1.8v device. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory architecture pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
device and array organization figure 9: array organization C mt29f4g08 (x8) cache register data register 2048 blocks per plane 4096 blocks per device 1 block 1 block dq0 dq7 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 2048 blocks = 2112mb 1 device = 2112mb x 2 planes = 4224mb plane of even-numbered blocks (0, 2, 4, 6, ..., 4092, 4094) plane of odd-numbered blocks (1, 3, 5, 7, ..., 4093, 4095) 64 2048 64 2112 bytes 2112 bytes 64 64 2048 2048 2048 table 2: array addressing C mt29f4g08 (x8) cycle i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low ba17 ba16 notes: 1. block address concatenated with page address = actual page address. cax = column ad- dress; pax = page address; bax = block address. 2. if ca11 is 1, then ca[10:6] must be 0. 3. ba6 controls plane selection. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory device and array organization pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 10: array organization C mt29f4g16 (x16) cache register data register 2048 blocks per plane 4096 blocks per device 1 block 1 block 1 page = (1k + 32 words) 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 plane = (64k + 2k) words x 2048 blocks = 2112mb 1 device = 2112mb x 2 planes = 4224mb plane of even-numbered blocks (0, 2, 4, 6, ..., 4092, 4094) plane of odd-numbered blocks (1, 3, 5, 7, ..., 4093, 4095) 32 1024 32 1056 words dq0 dq15 1056 words 32 32 1024 1024 1024 table 3: array addressing C mt29f4g16 (x16) cycle i/o[15:8] i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low ba17 ba16 notes: 1. block address concatenated with page address = actual page address. cax = column ad- dress; pax = page address; bax = block address. 2. if ca10 = 1, then ca[9:5] must be 0. 3. ba6 controls plane selection. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory device and array organization pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 11: array organization C mt29f8g08 and mt29f16g08 (x8) cache register data register 2048 blocks per plane 4096 blocks per die 1 block 1 block plane 0: even- numbered blocks (0, 2, 4, 6, ..., 4092, 4094) 1 plane 1: odd- numbered blocks (1, 3, 5, 7, ..., 4093, 4095) plane 0: even- numbered blocks (4096, 4098, ..., 8188, 8190) plane 1: odd- numbered blocks (4097, 4099, ..., 8189, 8191) 64 2048 64 2112 bytes 2112 bytes 64 64 2048 2048 2048 1 block 1 block 64 2048 64 2112 bytes 2112 bytes 64 64 2048 2048 2048 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 2048 blocks = 2112mb 1 die = 2112mb x 2 planes = 4224mb 1 device = 4224mb x 2 die = 8448mb i/o0 i/o7 die 0 die 1 note: 1. die 0, plane 0: ba18 = 0; ba6 = 0. die 0, plane 1: ba18 = 0; ba6 = 1. die 1, plane 0: ba18 = 1; ba6 = 0. die 1, plane 1: ba18 = 1; ba6 = 1. table 4: array addressing C mt29f8g08 and mt29f16g08 (x8) cycle i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low ba18 3 ba17 ba16 notes: 1. cax = column address; pax = page address; bax = block address. 2. if ca11 is 1, then ca[10:6] must be 0. 3. die address boundary: 0 = 0C4gb; 1 = 4gbC8gb. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory device and array organization pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 12: array organization C mt29f8g16 (x16) cache register data register 2048 blocks per plane 4096 blocks per die 1 block 1 block plane 0: even- numbered blocks (0, 2, 4, 6, ..., 4092, 4094) 1 plane 1: odd- numbered blocks (1, 3, 5, 7, ..., 4093, 4095) plane 0: even- numbered blocks (4096, 4098, ..., 8188, 8190) plane 1: odd- numbered blocks (4097, 4099, ..., 8189, 8191) 32 1024 32 1056 words 1056 words 32 32 1024 1024 1024 1 block 1 block 32 1024 32 1056 words 1056 words 32 32 1024 1024 1024 1 page = (1k + 32 words) 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 plane = (128k + 4k) bytes x 2048 blocks = 2112mb 1 die = 2112mb x 2 planes = 4224mb 1 device = 4224mb x 2 die = 8448mb i/o0 i/o7 die 0 die 1 note: 1. die 0, plane 0: ba18 = 0; ba6 = 0. die 0, plane 1: ba18 = 0; ba6 = 1. die 1, plane 0: ba18 = 1; ba6 = 0. die 1, plane 1: ba18 = 1; ba6 = 1. table 5: array addressing C mt29f8g16 ( x16) cycle i/o[15:8] i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 pa8 fifth low low low low low low ba18 3 ba17 ba16 notes: 1. block address concatenated with page address = actual page address. cax = column ad- dress; pax = page address; bax = block address. 2. if ca10 = 1, then ca[9:5] must be 0. 3. die address boundary: 0 = 0C4gb; 1 = 4gbC8gb. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory device and array organization pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
asynchronous interface bus operation the bus on the device is multiplexed. data i/o, addresses, and commands all share the same pins. i/o[15:8] are used only for data in the x16 configuration. addresses and commands are always supplied on i/o[7:0]. the command sequence typically consists of a command latch cycle, address input cycles, and one or more data cycles, either read or write. table 6: asynchronous interface mode selection mode 1 ce# cle ale we# re# i/ox wp# standby 2 h x x x x x 0v/v cc command input l h l h x h address input l l h h x h data input l l l h x h data output l l l h x x write protect x x x x x x l notes: 1. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . 2. wp# should be biased to cmos low or high for standby. asynchronous enable/standby when the device is not performing an operation, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power con- sumption. the ce# dont care operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flash is busy with internal operations. this capability is important for designs that require multiple nand flash devices on the same bus. a high cle signal indicates that a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. asynchronous commands an asynchronous command is written from i/o[7:0] to the command register on the ris- ing edge of we# when ce# is low, ale is low, cle is high, and re# is high. commands are typically ignored by die (luns) that are busy (rdy = 0); however, some commands, including read status (70h) and read status enhanced (78h), are accepted by die (luns) even when they are busy. for devices with a x16 interface, i/o[15:8] must be written with zeros when a command is issued. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 13: asynchronous command latch cycle we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls dont care micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
asynchronous addresses an asynchronous address is written from i/o[7:0] to the address register on the rising edge of we# when ce# is low, ale is high, cle is low, and re# is high. bits that are not part of the address space must be low (see device and array organiza- tion). the number of cycles required for each command varies. refer to the command descriptions to determine addressing requirements. addresses are typically ignored by die (luns) that are busy (rdy = 0); however, some addresses are accepted by die (luns) even when they are busy; for example, like ad- dress cycles that follow the read status enhanced (78h) command. figure 14: asynchronous address latch cycle we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 dont care undefined t wc micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
asynchronous data input data is written from i/o[7:0] to the cache register of the selected die (lun) on the rising edge of we# when ce# is low, ale is low, cle is low, and re# is high. data input is ignored by die (luns) that are not selected or are busy (rdy = 0). data is written to the data register on the rising edge of we# when ce#, cle, and ale are low, and the device is not busy. data is input on i/o[7:0] on x8 devices and on i/o[15:0] on x16 devices. figure 15: asynchronous data input cycles we# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in m+1 d in n dont care t wc d in m micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
asynchronous data output data can be output from a die (lun) if it is in a ready state. data output is supported following a read operation from the nand flash array. data is output from the cache register of the selected die (lun) to i/o[7:0] on the falling edge of re# when ce# is low, ale is low, cle is low, and we# is high. if the host controller is using a t rc of 30ns or greater, the host can latch the data on the rising edge of re# (see the figure below for proper timing). if the host controller is using a t rc of less than 30ns, the host can latch the data on the next falling edge of re#. using the read status enhanced (78h) command prevents data contention follow- ing an interleaved die (multi-lun) operation. after issuing the read status en- hanced (78h) command, to enable data output, issue the read mode (00h) com- mand. data output requests are typically ignored by a die (lun) that is busy (rdy = 0); howev- er, it is possible to output data from the status register even when a die (lun) is busy by first issuing the read status or read status enhanced (78h) command. figure 16: asynchronous data output cycles ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea dont care t rhz t chz t rhz t rhoh rdy t coh d out d out d out micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 17: asynchronous data output cycles (edo mode) d out d out d out ce# re# i/ox rdy t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz dont care write protect# the write protect# (wp#) signal enables or disables program and erase operations to a target. when wp# is low, program and erase operations are disabled. when wp# is high, program and erase operations are enabled. it is recommended that the host drive wp# low during power-on until v cc is stable to prevent inadvertent program and erase operations (see device initialization for ad- ditional details). wp# must be transitioned only when the target is not busy and prior to beginning a command sequence. after a command sequence is complete and the target is ready, wp# can be transitioned. after wp# is transitioned, the host must wait t ww before issu- ing a new command. the wp# signal is always an active input, even when ce# is high. this signal should not be multiplexed with other signals. ready/busy# the ready/busy# (r/b#) signal provides a hardware method of indicating whether a tar- get is ready or busy. a target is busy when one or more of its die (luns) are busy (rdy = 0). a target is ready when all of its die (luns) are ready (rdy = 1). because each die (lun) contains a status register, it is possible to determine the independent status of each die (lun) by polling its status register instead of using the r/b# signal (see sta- tus operations for details regarding die (lun) status). this signal requires a pull-up resistor, rp, for proper operation. r/b# is high when the target is ready, and transitions low when the target is busy. the signal's open-drain micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
driver enables multiple r/b# outputs to be or-tied. typically, r/b# is connected to an interrupt pin on the system controller. the combination of rp and capacitive loading of the r/b# circuit determines the rise time of the r/b# signal. the actual value used for rp depends on the system timing re- quirements. large values of rp cause r/b# to be delayed significantly. between the 10% and 90% points on the r/b# waveform, the rise time is approximately two time con- stants (tc). t c = r c where r = rp (resistance of pull-up resistor), and c = total capacitive load. the fall time of the r/b# signal is determined mainly by the output impedance of the r/b# signal and the total load capacitance. approximate rp values using a circuit load of 100pf are provided in figure 23 (page 29). the minimum value for rp is determined by the output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . rp = v cc (max) - v ol (max) i ol + il where il is the sum of the input currents of all devices tied to the r/b# pin. figure 18: read/busy# open drain rp v cc r/b# open drain output i ol v ss device micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 19: t fall and t rise (3.3v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 C1 0 2 4 0 2 4 6 t fall t rise v cc 3.3v t c v notes: 1. t fall and t rise calculated at 10% and 90% points. 2. t rise dependent on external capacitance and resistive loading and output transistor im- pedance. 3. t rise primarily dependent on external pull-up resistor and external capacitive loading. 4. t fall = 10ns at 3.3v. 5. see tc values in figure 23 (page 29) for approximate rp value and tc. figure 20: t fall and t rise (1.8v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise v cc 1.8v t c v notes: 1. t fall and t rise are calculated at 10% and 90% points. 2. t rise is primarily dependent on external pull-up resistor and external capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 23 (page 29) for tc and approximate rp value. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 21: i ol vs. rp (v cc = 3.3v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 400 0 6000 8000 10,000 12,000 i ol at v cc (max) rp ( ) i (ma) figure 22: i ol vs. rp (1.8v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000 rp ( ) i (ma) i ol at v cc (max) micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 23: tc vs. rp 1200 1000 800 600 400 200 0 0 2000 4000 6000 8000 10,000 12,000 i ol at v cc (max) rc = tc c = 100pf rp ( ) t(ns) micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface bus operation pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
device initialization micron nand flash devices are designed to prevent data corruption during power transitions. v cc is internally monitored. (the wp# signal supports additional hardware protection during power transitions.) when ramping v cc , use the following procedure to initialize the device: 1. ramp v cc . 2. the host must wait for r/b# to be valid and high before issuing reset (ffh) to any target. the r/b# signal becomes valid when 50s has elapsed since the begin- ning the v cc ramp, and 10s has elapsed since v cc reaches v cc (min). 3. if not monitoring r/b#, the host must wait at least 100s after v cc reaches v cc (min). if monitoring r/b#, the host must wait until r/b# is high. 4. the asynchronous interface is active by default for each target. each lun draws less than an average of 10ma (i st ) measured over intervals of 1ms until the reset (ffh) command is issued. 5. the reset (ffh) command must be the first command issued to all targets (ce#s) after the nand flash device is powered on. each target will be busy for 1ms after a reset command is issued. the reset busy time can be monitored by polling r/b# or issuing the read status (70h) command to poll the status register. 6. the device is now initialized and ready for normal operation. figure 24: r/b# power-on behavior reset (ffh) is issued 50s (min) 100s (max) invalid 10s (max) v cc ramp starts v cc r/b# v cc = v cc (min) micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory device initialization pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
command definitions table 7: command set command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes reset operations reset ffh 0 C C yes yes identification operation read id 90h 1 C C no no read parameter page ech 1 C C no no read unique id edh 1 C C no no feature operations get features eeh 1 C C no no set features efh 1 4 C no no status operations read status 70h 0 C C yes read status en- hanced 78h 3 C C yes yes column address operations random data read 05h 2 C e0h no yes random data input 85h 2 optional C no yes program for internal data move 85h 5 optional C no yes 3 read operations read mode 00h 0 C C no yes read page 00h 5 C 30h no yes read page cache se- quential 31h 0 C C no yes 4, 5 read page cache random 00h 5 C 31h no yes 4, 5 read page cache last 3fh 0 C C no yes 4, 5 program operations program page 80h 5 yes 10h no yes program page cache 80h 5 yes 15h no yes 4, 6 erase operations erase block 60h 3 C d0h no yes internal data move operations read for internal data move 00h 5 C 35h no yes 3 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory command definitions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 7: command set (continued) command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes program for inter- nal data move 85h 5 optional 10h no yes block lock operations block unlock low 23h 3 C C no yes block unlock high 24h 3 C C no yes block lock 2ah C C C no yes block lock-tight 2ch C C C no yes block lock read status 7ah 3 C C no yes one-time programmable (otp) operations otp data lock by page (onfi) 80h 5 no 10h no no 7 otp data program (onfi) 80h 5 yes 10h no no 7 otp data read (onfi) 00h 5 no 30h no no 7 notes: 1. busy means rdy = 0. 2. these commands can be used for interleaved die (multi-lun) operations (see interleaved die (multi-lun) operations (page 106)). 3. do not cross plane address boundaries when using read for internal data move and program for internal data move. 4. these commands supported only with ecc disabled. 5. issuing a read page cache series (31h, 00h-31h, 3fh) command when the array is busy (rdy = 1, ardy = 0) is supported if the previous command was a read page (00h-30h) or read page cache series command; otherwise, it is prohibited. 6. issuing a program page cache (80h-15h) command when the array is busy (rdy = 1, ardy = 0) is supported if the previous command was a program page cache (80h-15h) command; otherwise, it is prohibited. 7. otp commands can be entered only after issuing the set features command with the feature address. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory command definitions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 8: two-plane command set note 4 applies to all parameters and conditions command com- mand cycle #1 number of valid address cycles com- mand cycle #2 number of valid address cycles com- mand cycle #3 valid while selected lun is busy valid while other luns are busy notes read page two- plane 00h 5 00h 5 30h no yes read for two- plane internal data move 00h 5 00h 5 35h no yes 1 random data read two-plane 06h 5 e0h C C no yes 2 program page two-plane 80h 5 11h-80h 5 10h no yes program page cache mode two- plane 80h 5 11h-80h 5 15h no yes program for two-plane inter- nal data move 85h 5 11h-85h 5 10h no yes 1 block erase two- plane 60h 3 d1h-60h 3 d0h no yes 3 notes: 1. do not cross plane boundaries when using read for internal data move two- plane or program for two-plane internal data move. 2. the random data read two-plane command is limited to use with the page read two-plane command. 3. d1h command can be omitted. 4. these commands supported only with ecc disabled. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory command definitions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
reset operations reset (ffh) the reset command is used to put the memory device into a known condition and to abort the command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partially erased or programmed, and is in- valid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register. the reset command must be issued to all ce#s as the first command after power-on. the device will be busy for a maximum of 1ms. figure 25: reset (ffh) operation cycle type i/o[7:0] r/b# t rst t wb ff command micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory reset operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
identification operations read id (90h) the read id (90h) command is used to read identifier codes programmed into the tar- get. this command is accepted by the target only when all die (luns) on the target are idle. writing 90h to the command register puts the target in read id mode. the target stays in this mode until another valid command is issued. when the 90h command is followed by an 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer id, device configuration, and part-spe- cific information. when the 90h command is followed by a 20h address cycle, the target returns the 4-byte onfi identifier code. figure 26: read id (90h) with 00h address operation cycle type i/o[7:0] t whr command 90h 00h byte 0 byte 1 byte 2 byte 3 address d out d out d out d out d out byte 4 note: 1. see the read id parameter tables for byte definitions. figure 27: read id (90h) with 20h address operation cycle type i/o[7:0] t whr command 90h 20h 4fh 4eh 46h 49h address d out d out d out d out note: 1. see read id parameter tables for byte definitions. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory identification operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read id parameter tables table 9: read id parameters for address 00h b = binary; h = hexadecimal options i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 value byte 0 C manufacturer id manufacturer micron 0 0 1 0 1 1 0 0 2ch byte 1 C device id mt29f4g08abada 4gb, x8, 3.3v 1 1 0 1 1 1 0 0 dch mt29f4g16abada 4gb, x16, 3.3v 1 1 0 0 1 1 0 0 cch mt29f4g08abbda 4gb, x8, 1.8v 1 0 1 0 1 1 0 0 ach mt29f4g16abbda 4gb, x16, 1.8v 1 0 1 1 1 1 0 0 bch mt29f8g08adbda 8gb, x8, 1.8v 1 0 1 0 0 0 1 1 a3h mt29f8g16adbda 8gb, x16, 1.8v 1 0 1 1 0 0 1 1 b3h mt29f8g08adada 8gb, x8, 3.3v 1 1 0 1 0 0 1 1 d3h mt29f8g16adada 8gb, x16, 3.3v 1 1 0 0 0 0 1 1 c3h mt29f16g08ajada 16gb, x8, 3.3v 1 1 0 1 0 0 1 1 d3h byte 2 number of die per ce 1 0 0 00b 2 0 1 01b cell type slc 0 0 00b number of simultaneously programmed pages 2 0 1 01b interleaved operations be- tween multiple die not supported 0 0b cache programming supported 1 1b byte value mt29f4g08abada 1 0 0 1 0 0 0 0 90h mt29f4g16abada 1 0 0 1 0 0 0 0 90h mt29f4g08abbda 1 0 0 1 0 0 0 0 90h mt29f4g16abbda 1 0 0 1 0 0 0 0 90h mt29f8g08adbda 1 1 0 1 0 0 0 1 d1h mt29f8g16adbda 1 1 0 1 0 0 0 1 d1h mt29f8g08adada 1 1 0 1 0 0 0 1 d1h mt29f8g16adada 1 1 0 1 0 0 0 1 d1h mt29f16g08ajada 1 1 0 1 0 0 0 1 d1h byte 3 page size 2kb 0 1 01b spare area size (bytes) 64b 1 1b block size (without spare) 128kb 0 1 01b organization x8 0 0b x16 1 1b micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read id parameter tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 9: read id parameters for address 00h (continued) b = binary; h = hexadecimal options i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 value serial access (min) 1.8v 25ns 0 0 0xxx0b 3.3v 20ns 1 0 1xxx0b byte value mt29f4g08abada 1 0 0 1 0 1 0 1 95h mt29f4g16abada 1 1 0 1 0 1 0 1 d5h mt29f4g08abbda 0 0 0 1 0 1 0 1 15h mt29f4g16abbda 0 1 0 1 0 1 0 1 55h mt29f8g08adbda 0 0 0 1 0 1 0 1 15h mt29f8g16adbda 0 1 0 1 0 1 0 1 55h mt29f8g08adada 1 0 0 1 0 1 0 1 95h mt29f8g16adada 1 1 0 1 0 1 0 1 d5h mt29f16g08ajada 1 0 0 1 0 1 0 1 95h byte 4 internal ecc level 4-bit ecc/512 (main) + 4 (spare) + 8 (parity) bytes 1 0 10b planes per ce# 2 0 1 01b 4 1 0 10b plane size 2gb 1 0 1 101b internal ecc ecc disabled 0 0b ecc enabled 1 1b byte value mt29f4g08abada 0 1 0 1 0 1 1 0 56h mt29f4g16abada 0 1 0 1 0 1 1 0 56h mt29f4g08abbda 0 1 0 1 0 1 1 0 56h mt29f4g16abbda 0 1 0 1 0 1 1 0 56h mt29f8g08adbda 0 1 0 1 1 0 1 0 5ah mt29f8g16adbda 0 1 0 1 1 0 1 0 5ah mt29f8g08adada 0 1 0 1 1 0 1 0 5ah mt29f8g16adada 0 1 0 1 1 0 1 0 5ah mt29f16g08ajada 0 1 0 1 1 0 1 0 5ah micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read id parameter tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 10: read id parameters for address 20h h = hexadecimal byte options i/07 i/06 i/05 i/04 i/03 i/02 i/01 i/00 value 0 o 0 1 0 0 1 1 1 1 4fh 1 n 0 1 0 0 1 1 1 0 4eh 2 f 0 1 0 0 0 1 1 0 46h 3 i 0 1 0 0 1 0 0 1 49h 4 undefined x x x x x x x x xxh micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read id parameter tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read parameter page (ech) the read parameter page (ech) command is used to read the onfi parameter page programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing ech to the command register puts the target in read parameter page mode. the target stays in this mode until another valid command is issued. when the ech command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. use of the read status enhanced (78h) command is prohibited while the target is busy and during data output. a minimum of three copies of the parameter page are stored in the device. each param- eter page is 256 bytes. if desired, the random data read (05h-e0h) command can be used to change the location of data output. figure 28: read parameter (ech) operation cycle type i/o[7:0] r/b# t wb t r t rr command address d out ech 00h p0 0 p1 0 d out d out p0 1 d out d out p1 1 d out micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read parameter page (ech) pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
parameter page data structure tables table 11: parameter page data structure byte description value 0C3 parameter page signature 4fh, 4eh, 46h, 49h 4C5 revision number 02h, 00h 6C7 features supported mt29f4g08abbdah4 18h, 00h mt29f4g08abbdahc 18h, 00h mt29f4g16abbdahc 19h, 00h mt29f4g16abbdah4 19h, 00h mt29f8g08adbdah4 1ah, 00h mt29f8g16adbdah4 1bh, 00h mt29f4g08abadawp 18h, 00h MT29F4G08ABADAH4 18h, 00h mt29f4g16abadawp 19h, 00h mt29f4g16abadah4 19h, 00h mt29f8g08adadah4 1ah, 00h mt29f8g16adadah4 1bh, 00h mt29f16g08ajadawp 1ah, 00h 8C9 optional commands supported 3fh, 00h 10C31 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 32C43 device manufacturer 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: parameter page data structure (continued) byte description value 44C63 device model mt29f4g08abbdah4 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f4g08abbdahc 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h mt29f4g16abbdahc 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h mt29f4g16abbdah4 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f8g08adbdah4 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f8g16adbdah4 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f4g08abadawp 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20 MT29F4G08ABADAH4 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f4g16abadawp 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20h mt29f4g16abadah4 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f8g08adadah4 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f8g16adadah4 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h mt29f16g08ajadawp 4dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 41h, 4ah, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h 64 manufacturer id 2ch 65C66 date code 00h, 00h 67C79 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80C83 number of data bytes per page 00h, 08h, 00h, 00h 84C85 number of spare bytes per page 40h, 00h 86C89 number of data bytes per partial page 00h, 02h, 00h, 00h 90C91 number of spare bytes per partial page 10h, 00h 92C95 number of pages per block 40h, 00h, 00h, 00h 96C99 number of blocks per unit 00h, 10h, 00h, 00h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: parameter page data structure (continued) byte description value 100 number of logical units mt29f4g08abbdah4 01h mt29f4g08abbdahc 01h mt29f4g16abbdahc 01h mt29f4g16abbdah4 01h mt29f8g08adbdah4 02h mt29f8g16adbdah4 02h mt29f4g08abadawp 01h MT29F4G08ABADAH4 01h mt29f4g16abadawp 01h mt29f4g16abadah4 01h mt29f8g08adadah4 02h mt29f8g16adadah4 02h mt29f16g08ajadawp 04h 101 number of address cycles 23h 102 number of bits per cell 01h 103C104 bad blocks maximum per unit 50h, 00h 105C106 C C 107 guaranteed valid blocks at beginning of target 01h 108C109 block endurance for guaranteed valid blocks 00h, 00h 110 number of programs per page 04h 111 partial programming attributes 00h 112 number of bits ecc bits 04h 113 number of interleaved address bits 01h 114 interleaved operation attributes 0eh 115C127 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: parameter page data structure (continued) byte description value 128 i/o pin capacitance mt29f4g08abbdah4 0ah mt29f4g08abbdahc 0ah mt29f4g16abbdahc 0ah mt29f4g16abbdah4 0ah mt29f8g08adbdah4 14h mt29f8g16adbdah4 14h mt29f4g08abadawp 0ah MT29F4G08ABADAH4 0ah mt29f4g16abadawp 0ah mt29f4g16abadah4 0ah mt29f8g08adadah4 14h mt29f8g16adadah4 14h mt29f16g08ajadawp 28h 129C130 timing mode support mt29f4g08abbdah4 1fh, 00h mt29f4g08abbdahc 1fh, 00h mt29f4g16abbdahc 1fh, 00h mt29f4g16abbdah4 1fh, 00h mt29f8g08adbdah4 1fh, 00h mt29f8g16adbdah4 1fh, 00h mt29f4g08abadawp 3fh, 00h MT29F4G08ABADAH4 3fh, 00h mt29f4g16abadawp 3fh, 00h mt29f4g16abadah4 3fh, 00h mt29f8g08adadah4 3fh, 00h mt29f8g16adadah4 3fh, 00h mt29f16g08ajadawp 3fh, 00h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: parameter page data structure (continued) byte description value 131C132 program cache timing mode support mt29f4g08abbdah4 1fh, 00h mt29f4g08abbdahc 1fh, 00h mt29f4g16abbdahc 1fh, 00h mt29f4g16abbdah4 1fh, 00h mt29f8g08adbdah4 1fh, 00h mt29f8g16adbdah4 1fh, 00h mt29f4g08abadawp 3fh, 00h MT29F4G08ABADAH4 3fh, 00h mt29f4g16abadawp 3fh, 00h mt29f4g16abadah4 3fh, 00h mt29f8g08adadah4 3fh, 00h mt29f8g16adadah4 3fh, 00h mt29f16g08ajadawp 3fh, 00h 133C134 t prog (max) page program time 58h, 02h 135C136 t bers (max) block erase time b8h, 0bh 137C138 t r (max) page read time 19h, 00h 139C140 t ccs (min) 64h, 00h 141C163 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 164C165 vendor-specific revision number 01h, 00h 166C253 vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h,0ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h 254C255 integrity crc set at test 256C511 value of bytes 0C255 512C767 value of bytes 0C255 768+ additional redundant parameter pages micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
bare die parameter page data structure tables table 12: parameter page data structure byte description value 0C3 parameter page signature 4fh, 4eh, 46h, 49h 4C5 revision number 02h, 00h 6C7 features supported mt29f4g08abbda3w 18h, 00h mt29f4g16abbda3w 19h, 00h mt29f8g08adbda3w 1ah, 00h mt29f8g16adbda3w 1bh, 00h mt29f4g08abada3w 18h, 00h mt29f4g16abada3w 19h, 00h mt29f8g08adada3w 1ah, 00h mt29f8g16adada3w 1bh, 00h 8C9 optional commands supported 3fh, 00h 10C31 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 32C43 device manufacturer 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h 44C63 device model mt29f4g08abbda3w 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f4g16abbda3w 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f8g08adbda3w 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f8g16adbda3w 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f4g08abada3w 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f4g16abada3w 4dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f8g08adada3w 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h mt29f8g16adada3w 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h 64 manufacturer id 2ch 65C66 date code 00h, 00h 67C79 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80C83 number of data bytes per page 00h, 08h, 00h, 00h 84C85 number of spare bytes per page 40h, 00h 86C89 number of data bytes per partial page 00h, 02h, 00h, 00h 90C91 number of spare bytes per partial page 10h, 00h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory bare die parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: parameter page data structure (continued) byte description value 92C95 number of pages per block 40h, 00h, 00h, 00h 96C99 number of blocks per unit 00h, 10h, 00h, 00h 100 number of logical units mt29f4g08abbda3w 01h mt29f4g16abbda3w 01h mt29f8g08adbda3w 02h mt29f8g16adbda3w 02h mt29f4g08abada3w 01h mt29f4g16abada3w 01h mt29f8g08adada3w 02h mt29f8g16adada3w 02h 101 number of address cycles 23h 102 number of bits per cell 01h 103C104 bad blocks maximum per unit 50h, 00h 105C106 block endurance 01h, 05h 107 guaranteed valid blocks at beginning of target 01h 108C109 block endurance for guaranteed valid blocks 00h, 00h 110 number of programs per page 04h 111 partial programming attributes 00h 112 number of bits ecc bits 04h 113 number of interleaved address bits 01h 114 interleaved operation attributes 0eh 115C127 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 128 i/o pin capacitance mt29f4g08abbda3w 0ah mt29f4g16abbda3w 0ah mt29f8g08adbda3w 14h mt29f8g16adbda3w 14h mt29f4g08abada3w 0ah mt29f4g16abada3w 0ah mt29f8g08adada3w 14h mt29f8g16adada3w 14h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory bare die parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: parameter page data structure (continued) byte description value 129C130 timing mode support mt29f4g08abbda3w 1fh, 00h mt29f4g16abbda3w 1fh, 00h mt29f8g08adbda3w 1fh, 00h mt29f8g16adbda3w 1fh, 00h mt29f4g08abada3w 3fh, 00h mt29f4g16abada3w 3fh, 00h mt29f8g08adada3w 3fh, 00h mt29f8g16adada3w 3fh, 00h 131C132 program cache timing mode support mt29f4g08abbda3w 1fh, 00h mt29f4g16abbda3w 1fh, 00h mt29f8g08adbda3w 1fh, 00h mt29f8g16adbda3w 1fh, 00h mt29f4g08abada3w 3fh, 00h mt29f4g16abada3w 3fh, 00h mt29f8g08adada3w 3fh, 00h mt29f8g16adada3w 3fh, 00h 133C134 t prog (max) page program time 58h, 02h 135C136 t bers (max) block erase time b8h, 0bh 137C138 t r (max) page read time 19h, 00h 139C140 t ccs (min) 64h, 00h 141C163 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 164C165 vendor-specific revision number 01h, 00h 166C253 vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h,0ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h 254C255 integrity crc set at test 256C511 value of bytes 0C255 512C767 value of bytes 0C255 768+ additional redundant parameter pages micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory bare die parameter page data structure tables pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read unique id (edh) the read unique id (edh) command is used to read a unique identifier programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing edh to the command register puts the target in read unique id mode. the tar- get stays in this mode until another valid command is issued. when the edh command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. after t r completes, the host enables data output mode to read the unique id. when the asynchronous interface is active, one data byte is output per re# toggle. sixteen copies of the unique id data are stored in the device. each copy is 32 bytes. the first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple- ment of the first 16 bytes. the host should xor the first 16 bytes with the second 16 bytes. if the result is 16 bytes of ffh, then that copy of the unique id data is correct. in the event that a non-ffh result is returned, the host can repeat the xor operation on a subsequent copy of the unique id data. if desired, the random data read (05h-e0h) command can be used to change the data output location. the upper eight i/os on a x16 device are not used and are a dont care for x16 devi- ces. figure 29: read unique id (edh) operation cycle type i/o[7:0] r/b# t wb t r t rr command address d out edh 00h u0 0 u1 0 d out d out u0 1 d out d out u1 1 d out micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read unique id (edh) pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
feature operations the set features (efh) and get features (eeh) commands are used to modify the target's default power-on behavior. these commands use a one-byte feature address to determine which subfeature parameters will be read or modified. each feature address (in the 00h to ffh range) is defined in below. the set features (efh) command writes subfeature parameters (p1Cp4) to the specified feature address. the get fea- tures command reads the subfeature parameters (p1Cp4) at the specified feature ad- dress. when a feature is set, by default it remains active until the device is power cycled. it is volatile. unless otherwise specified in the features table, once a device is set it remains set, even if a reset (ffh) command is issued. get/set features commands can be used after required reset to enable features before system boot rom process. internal ecc can be enabled/disabled using set features (efh). the set features command (efh), followed by address 90h, followed by four data bytes (only the first da- ta byte is used) will enable/disable internal ecc. the sequence to enable internal ecc with set features is efh(cmd)-90h(addr)- 08h(data)-00h(data)-00h(data)-00h(data)-wait( t feat). the sequence to disable internal ecc with set features is efh(cmd)-90h(addr)- 00h(data)-00h(data)-00h(data)-00h(data)-wait( t feat). the get features command is eeh. table 13: feature address definitions feature address definition 00h reserved 01h timing mode 02hC7fh reserved 80h programmable output drive strength 81h programmable rb# pull-down strength 82hCffh reserved 90h array operation mode micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory feature operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 14: feature address 90h C array operation mode subfeature parameter options 1/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 operation mode option normal reserved (0) 0 00h 1 otp operation reserved (0) 1 01h otp protection reserved (0) 1 1 03h disable ecc reserved (0) 0 0 0 0 00h 1 enable ecc reserved (0) 1 0 0 0 08h 1 p2 reserved reserved (0) 00h p3 reserved reserved (0) 00h p4 reserved reserved (0) 00h note: 1. these bits are reset to 00h on power cycle. set features (efh) the set features (efh) command writes the subfeature parameters (p1Cp4) to the specified feature address to enable or disable target-specific features. this command is accepted by the target only when all die (luns) on the target are idle. writing efh to the command register puts the target in the set features mode. the target stays in this mode until another command is issued. the efh command is followed by a valid feature address. the host waits for t adl before the subfeature parameters are input. when the asynchronous interface is active, one subfeature parameter is latched per rising edge of we#. after all four subfeature parameters are input, the target goes busy for t feat. the read status (70h) command can be used to monitor for command completion. feature address 01h (timing mode) operation is unique. if set features is used to modify the interface type, the target will be busy for t itc. figure 30: set features (efh) operation cycle type i/o[7:0] r/b# t adl command address efh fa d in d in d in d in p1 p2 p3 p4 t wb t feat micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory feature operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
get features (eeh) the get features (eeh) command reads the subfeature parameters (p1Cp4) from the specified feature address. this command is accepted by the target only when all die (luns) on the target are idle. writing eeh to the command register puts the target in get features mode. the target stays in this mode until another valid command is issued. when the eeh command is followed by a feature address, the target goes busy for t feat. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. after t feat completes, the host enables data output mode to read the subfeature pa- rameters. figure 31: get features (eeh) operation cycle type i/ox r/b# t wb t feat t rr command address d out eeh fa p1 p2 d out d out p3 p4 d out micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory feature operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 15: feature addresses 01h: timing mode subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 timing mode mode 0 (default) reserved (0) 0 0 0 00h 1, 2 mode 1 reserved (0) 0 0 1 01h 2 mode 2 reserved (0) 0 1 0 02h 2 mode 3 reserved (0) 0 1 1 03h 2 mode 4 reserved (0) 1 0 0 04h 2 mode 5 reserved (0) 1 0 1 05h 3 p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h notes: 1. the timing mode feature address is used to change the default timing mode. the timing mode should be selected to indicate the maximum speed at which the device will re- ceive commands, addresses, and data cycles. the five supported settings for the timing mode are shown. the default timing mode is mode 0. the device returns to mode 0 when the device is power cycled. supported timing modes are reported in the parame- ter page. 2. supported for both 1.8v and 3.3v. 3. supported for 3.3v only. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory feature operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 16: feature addresses 80h: programmable i/o drive strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 i/o drive strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h note: 1. the programmable drive strength feature address is used to change the default i/o drive strength. drive strength should be selected based on expected loading of the memory bus. this table shows the four supported output drive strength settings. the default drive strength is full strength. the device returns to the default drive strength mode when the device is power cycled. ac timing parameters may need to be relaxed if i/o drive strength is not set to full. table 17: feature addresses 81h: programmable r/b# pull-down strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 r/b# pull-down strength full (default) 0 0 00h 1 three-quarters 0 1 01h one-half 1 0 02h one-quarter 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h note: 1. this feature address is used to change the default r/b# pull-down strength. its strength should be selected based on the expected loading of r/b#. full strength is the default, power-on value. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory feature operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
status operations each die (lun) provides its status independently of other die (luns) on the same target through its 8-bit status register. after the read status (70h) or read status enhanced (78h) command is issued, status register output is enabled. the contents of the status register are returned on i/ o[7:0] for each data output request. when the asynchronous interface is active and status register output is enabled, changes in the status register are seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to toggle re# to see the status register update. while monitoring the status register to determine when a data transfer from the flash array to the data register ( t r) is complete, the host must issue the read mode (00h) command to disable the status register and enable data output (see read operations). the read status (70h) command returns the status of the most recently selected die (lun). to prevent data contention during or following an interleaved die (multi-lun) operation, the host must enable only one die (lun) for status output by using the read status enhanced (78h) command (see interleaved die (multi-lun) operations). with internal ecc enabled, a read status command is required after completion of the data transfer ( t r_ecc) to determine whether an uncorrectable read error occurred. table 18: status register definition sr bit program page program page cache mode page read page read cache mode block erase description 7 write protect write protect write protect write protect write protect 0 = protected 1 = not protected 6 rdy rdy 1 cache rdy rdy 1 cache rdy 0 = busy 1 = ready 5 ardy ardy 2 ardy ardy 2 ardy don't care 4 C C C C C don't care 3 C C rewrite recommended 3 C C 0 = normal or uncorrectable 1 = rewrite recommended 2 C C C C C don't care 1 failc (n - 1) failc (n - 1) reserved C C don't care 0 fail fail (n) fail 4 C fail 0 = successful program/ erase/read 1 = error in program/ erase/read notes: 1. status register bit 6 is 1 when the cache is ready to accept new data. r/b# follows bit 6. 2. status register bit 5 is 0 during the actual programming operation. if cache mode is used, this bit will be 1 when all internal operations are complete. 3. a status register bit defined as rewrite recommended signifies that the page includes acertain number of read errors per sector (512b (main) + 4b (spare) + 8b (parity). a re- writeof this page is recommended. (up to a 4-bit error has been corrected if internal ecc was enabled.) 4. a status register bit defined as fail signifies that an uncorrectable read error has oc- curred. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory status operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read status (70h) the read status (70h) command returns the status of the last-selected die (lun) on a target. this command is accepted by the last-selected die (lun) even when it is busy (rdy = 0). if there is only one die (lun) per target, the read status (70h) command can be used to return status following any nand command. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select the die (lun) that should report status. in this situation, using the read status (70h) command will result in bus contention, as two or more die (luns) could respond until the next operation is issued. the read status (70h) com- mand can be used following all single-die (lun) operations. figure 32: read status (70h) operation cycle type i/o[7:0] t whr command d out 70h sr read status enhanced (78h) the read status enhanced (78h) command returns the status of the addressed die (lun) on a target even when it is busy (rdy = 0). this command is accepted by all die (luns), even when they are busy (rdy = 0). writing 78h to the command register, followed by three row address cycles containing the page, block, and lun addresses, puts the selected die (lun) into read status mode. the selected die (lun) stays in this mode until another valid command is issued. die (luns) that are not addressed are deselected to avoid bus contention. the selected lun's status is returned when the host requests data output. the rdy and ardy bits of the status register are shared for all planes on the selected die (lun). the failc and fail bits are specific to the plane specified in the row address. the read status enhanced (78h) command also enables the selected die (lun) for data output. to begin data output following a read-series operation after the selected die (lun) is ready (rdy = 1), issue the read mode (00h) command, then begin data output. if the host needs to change the cache register that will output data, use the random data read two-plane (06h-e0h) command after the die (lun) is ready. use of the read status enhanced (78h) command is prohibited during the power- on reset (ffh) command and when otp mode is enabled. it is also prohibited follow- ing some of the other reset, identification, and configuration operations. see individual operations for specific details. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory status operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 33: read status enhanced (78h) operation cycle type i/ox t whr command address address address 78h r1 r2 r3 d out sr micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory status operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
column address operations the column address operations affect how data is input to and output from the cache registers within the selected die (luns). these features provide host flexibility for man- aging data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. when the asynchronous interface is active, column address operations can address any byte in the selected cache register. random data read (05h-e0h) the random data read (05h-e0h) command changes the column address of the se- lected cache register and enables data output from the last selected die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache read operations (rdy = 1; ardy = 0). writing 05h to the command register, followed by two column address cycles containing the column address, followed by the e0h command, puts the selected die (lun) into data output mode. after the e0h command cycle is issued, the host must wait at least t whr before requesting data output. the selected die (lun) stays in data output mode until another valid command is issued. in devices with more than one die (lun) per target, during and following interleaved die (multi-lun) operations, the read status enhanced (78h) command must be issued prior to issuing the random data read (05h-e0h). in this situation, using the random data read (05h-e0h) command without the read status enhanced (78h) command will result in bus contention because two or more die (luns) could output data. figure 34: random data read (05h-e0h) operation cycle type i/o[7:0] sr[6] command address address 05h command e0h c1 c2 t whr t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory column address operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
random data read two-plane (06h-e0h) the random data read two-plane (06h-e0h) command enables data output on the addressed dies (luns) cache register at the specified column address. this com- mand is accepted by a die (lun) when it is ready (rdy = 1; ardy = 1). writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by e0h, enables data output mode on the address luns cache register at the specified column address. after the e0h command cycle is issued, the host must wait at least t whr before requesting data output. the selected die (lun) stays in data output mode until another valid command is issued. following a two-plane read page operation, the random data read two-plane (06h-e0h) command is used to select the cache register to be enabled for data output. after data output is complete on the selected plane, the command can be issued again to begin data output on another plane. in devices with more than one die (lun) per target, after all of the die (luns) on the target are ready (rdy = 1), the random data read two-plane (06h-e0h) command can be used following an interleaved die (multi-lun) read operation. die (luns) that are not addressed are deselected to avoid bus contention. in devices with more than one die (lun) per target, during interleaved die (multi-lun) operations where more than one or more die (luns) are busy (rdy = 1; ardy = 0 or rdy = 0; ardy = 0), the read status enhanced (78h) command must be issued to the die (lun) to be selected prior to issuing the random data read two-plane (06h-e0h). in this situation, using the random data read two-plane (06h-e0h) command without the read status enhanced (78h) command will result in bus contention, as two or more die (luns) could output data. if there is a need to update the column address without selecting a new cache register or lun, the random data read (05h-e0h) command can be used instead. figure 35: random data read two-plane (06h-e0h) operation cycle type i/o[7:0] command address address 06h command e0h c1 c2 address address r1 r2 address r3 t whr t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory column address operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
random data input (85h) the random data input (85h) command changes the column address of the selec- ted cache register and enables data input on the last-selected die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also ac- cepted by the selected die (lun) during cache program operations (rdy = 1; ardy = 0). writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected die (lun) into data input mode. after the second address cycle is issued, the host must wait at least t adl before inputting data. the se- lected die (lun) stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the random data input (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following com- mands while data input is permitted: program page (80h-10h), program page cache (80h-15h), program for internal data move (85h-10h), and program for two-plane internal data move (85h-11h). in devices that have more than one die (lun) per target, the random data input (85h) command can be used with other commands that support interleaved die (multi- lun) operations. figure 36: random data input (85h) operation cycle type i/o[7:0] rdy command address address 85h c1 c2 t adl d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 as defined for page (cache) program as defined for page (cache) program micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory column address operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
program for internal data input (85h) the program for internal data input (85h) command changes the row address (block and page) where the cache register contents will be programmed in the nand flash array. it also changes the column address of the selected cache register and ena- bles data input on the specified die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache programming operations (rdy = 1; ardy = 0). write 85h to the command register. then write two column address cycles and three row address cycles. this updates the page and block destination of the selected device for the addressed lun and puts the cache register into data input mode. after the fifth address cycle is issued the host must wait at least t adl before inputting data. the selec- ted lun stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the program for internal data input (85h) command is allowed after the re- quired address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: program page (80h-10h), program page two-plane (80h-11h), program page cache (80h-15h), pro- gram for internal data move (85h-10h), and program for two-plane in- ternal data move (85h-11h). when used with these commands, the lun address and plane select bits are required to be identical to the lun address and plane select bits originally specified. the program for internal data input (85h) command enables the host to mod- ify the original page and block address for the data in the cache register to a new page and block address. in devices that have more than one die (lun) per target, the program for internal data input (85h) command can be used with other commands that support inter- leaved die (multi-lun) operations. the program for internal data input (85h) command can be used with the random data read (05h-e0h) or random data read two-plane (06h-e0h) commands to read and modify cache register contents in small sections prior to pro- gramming cache register contents to the nand flash array. this capability can reduce the amount of buffer memory used in the host controller. the random data input (85h) command can be used during the program for internal data move command sequence to modify one or more bytes of the origi- nal data. first, data is copied into the cache register using the 00h-35h command se- quence, then the random data input (85h) command is written along with the ad- dress of the data to be modified next. new data is input on the external data pins. this copies the new data into the cache register. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory column address operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 37: program for internal data input (85h) operation cycle type i/o[7:0] rdy command address address address address command 85h c1 c2 t adl d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 r1 r2 10h address r3 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory column address operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read operations the read page (00h-30h) command, when issued by itself, reads one page from the nand flash array to its cache register and enables data output for that cache register. during data output the following commands can be used to read and modify the data in the cache registers: random data read (05h-e0h) and random data input (85h). read cache operations to increase data throughput, the read page cache series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the nand flash array to the data register. to begin a read page cache sequence, begin by reading a page from the nand flash ar- ray to its corresponding cache register using the read page (00h-30h) command. r/b# goes low during t r and the selected die (lun) is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), issue either of these commands: ? read page cache sequential (31h) C copies the next sequential page from the nand flash array to the data register ? read page cache random (00h-31h) C copies the page specified in this command from the nand flash array to its corresponding data register after the read page cache series (31h, 00h-31h) command has been issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the next page begins copying data from the array to the data register. after t rcbsy, r/b# goes high and the dies (luns) status register bits indicate the device is busy with a cache operation (rdy = 1, ardy = 0). the cache register becomes available and the page requested in the read page cache operation is transferred to the data regis- ter. at this point, data can be output from the cache register, beginning at column ad- dress 0. the random data read (05h-e0h) command can be used to change the col- umn address of the data output by the die (lun). after outputting the desired number of bytes from the cache register, either an addi- tional read page cache series (31h, 00h-31h) operation can be started or the read page cache last (3fh) command can be issued. if the read page cache last (3fh) command is issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the data register is copied into the cache register. after t rcbsy, r/b# goes high and rdy = 1 and ardy = 1, indicating that the cache register is available and that the die (lun) is ready. data can then be output from the cache register, beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output. for read page cache series (31h, 00h-31h, 3fh), during the die (lun) busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh). when rdy = 1 and ardy = 0, the only valid commands during read page cache series (31h, 00h-31h) operations are status operations (70h, 78h), read mode (00h), read page cache series (31h, 00h-31h), random data read (05h-e0h), and reset (ffh). micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
two-plane read operations two-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. this is done by pre- pending one or more read page two-plane (00h-00h-30h) commands in front of the read page (00h-30h) command. when the die (lun) is ready, the random data read two-plane (06h-e0h) com- mand determines which plane outputs data. during data output, the following com- mands can be used to read and modify the data in the cache registers: random data read (05h-e0h) and random data input (85h). two-plane read cache operations two-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the nand flash array to the data register. this is done by prepending read page two-plane (00h-00h-30h) commands in front of the page read cache random (00h-31h) command. to begin a two-plane read page cache sequence, begin by issuing a read page two- plane operation using the read page two-plane (00h-00h-30h) and read page (00h-30h) commands. r/b# goes low during t r and the selected die (lun) is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), issue either of these commands: ? read page cache sequential (31h) C copies the next sequential pages from the previously addressed planes from the nand flash array to the data registers. ? read page two-plane (00h-00h-30h) [in some cases, followed by read page cache random (00h-31h)] C copies the pages specified from the nand flash array to the corresponding data registers. after the read page cache series (31h, 00h-31h) command has been issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the next pages begin copying data from the array to the data registers. after t rcbsy, r/b# goes high and the luns status register bits indicate the device is busy with a cache operation (rdy = 1, ardy = 0). the cache registers become available and the pa- ges requested in the read page cache operation are transferred to the data registers. issue the random data read two-plane (06h-e0h) command to determine which cache register will output data. after data is output, the random data read two- plane (06h-e0h) command can be used to output data from other cache registers. af- ter a cache register has been selected, the random data read (05h-e0h) command can be used to change the column address of the data output. after outputting data from the cache registers, either an additional two-plane read cache series (31h, 00h-31h) operation can be started or the read page cache last (3fh) command can be issued. if the read page cache last (3fh) command is issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the data registers are cop- ied into the cache registers. after t rcbsy, r/b# goes high and rdy = 1 and ardy = 1, indicating that the cache registers are available and that the die (lun) is ready. issue the random data read two-plane (06h-e0h) command to determine which cache register will output data. after data is output, the random data read two-plane (06h-e0h) command can be used to output data from other cache registers. after a cache register has been selected, the random data read (05h-e0h) command can be used to change the column address of the data output. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
for read page cache series (31h, 00h-31h, 3fh), during the die (lun) busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh). when rdy = 1 and ardy = 0, the only valid commands during read page cache series (31h, 00h-31h) operations are status operations (70h, 78h), read mode (00h), two-plane read cache series (31h, 00h-00h-30h, 00h-31h), random data read (06h-e0h, 05h-e0h), and reset (ffh). read mode (00h) the read mode (00h) command disables status output and enables data output for the last-selected die (lun) and cache register after a read operation (00h-30h, 00h-3ah, 00h-35h) has been monitored with a status operation (70h, 78h). this com- mand is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accep- ted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) prior to issuing the read mode (00h) com- mand. this prevents bus contention. read page (00h-30h) the read page (00hC30h) command copies a page from the nand flash array to its respective cache register and enables data output. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to read a page from the nand flash array, write the 00h command to the command register, then write n address cycles to the address registers, and conclude with the 30h command. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. if the status opera- tions are used to monitor the lun's status, when the die (lun) is ready (rdy = 1, ardy = 1), the host disables status output and enables data output by issuing the read mode (00h) command. when the host requests data output, output begins at the column address specified. during data output the random data read (05h-e0h) command can be issued. when internal ecc is enabled, the read status (70h) command is required after the completion of the data transfer ( t r_ecc) to determine whether an uncorrectable read error occured. ( t r_ecc is the data transferred with internal ecc enabled.) in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations the read status enhanced (78h) command must be used to select only one die (lun) prior to the issue of the read mode (00h) command. this prevents bus contention. the read page (00h-30h) command is used as the final command of a two-plane read operation. it is preceded by one or more read page two-plane (00h-00h-30h) com- mands. data is transferred from the nand flash array for all of the addressed planes to their respective cache registers. when the die (lun) is ready (rdy = 1, ardy = 1), data output is enabled for the cache register linked to the plane addressed in the read page (00h-30h) command. when the host requests data output, micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
output begins at the column address last specified in the read page (00h-30h) com- mand. the random data read two-plane (06h-e0h) command is used to enable data output in the other cache registers. figure 38: read page (00h-30h) operation cycle type i/o[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 30h d out d n d out d n+1 d out d n+2 figure 39: read page (00h-30h) operation with internal ecc enabled i/o[7:0] rdy t r_ecc 00h 70h 30h 00h status sr bit 0 = 0 read successful sr bit 1 = 0 read error d out (serial access) address address address address address read page cache sequential (31h) the read page cache sequential (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 31h to the command register. after this command is is- sued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point, data can be output from the cache register beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output from the cache register. the read page cache sequential (31h) command can be used to cross block boundaries. if the read page cache sequential (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logi- cal block in which the 31h command was issued. do not issue the read page cache sequential (31h) to cross die (lun) boundaries. instead, issue the read page cache last (3fh) command. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 40: read page cache sequential (31h) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command d out d out d out command d out 31h rr t wb command 30h t wb t rcbsy t rr d0 dn 31h d0 command address x5 00h page address m page m page m+1 t r read page cache random (00h-31h) the read page cache random (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 00h to the command register, then write n address cycles to the address register, and conclude by writing 31h to the command register. the col- umn address in the address specified is ignored. the die (lun) address must match the same die (lun) address as the previous read page (00h-30h) command or, if applica- ble, the previous read page cache random (00h-31h) command. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is availa- ble and that the specified page is copying from the nand flash array to the data regis- ter. at this point, data can be output from the cache register beginning at column ad- dress 0. the random data read (05h-e0h) command can be used to change the col- umn address of the data being output from the cache register. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations the read status enhanced (78h) command fol- lowed by the read mode (00h) command must be used to select only one die (lun) and prevent bus contention. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 41: read page cache random (00h-31h) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command d out d out d out 31h rr t wb command 30h d0 dn command address x5 00h command 00h page address m address x5 page address n command 00h page m t r 1 cycle type i/o[7:0] rdy d out command d out t wb t rcbsy t rr dn 31h d0 command 00h address x5 page address p page n 1 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read page cache last (3fh) the read page cache last (3fh) command ends the read page cache sequence and copies a page from the data register to the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue the read page cache last (3fh) command, write 3fh to the command reg- ister. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is ready (rdy = 1, ardy = 1). at this point, data can be output from the cache register, be- ginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output from the cache register. in devices that have more than one lun per target, during and following interleaved die (multi-lun) operations the read status enhanced (78h) command followed by the read mode (00h) command must be used to select only one die (lun) and pre- vent bus contention. figure 42: read page cache last (3fh) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command command d out d out d out d out d out d out 31h t wb t rcbsy t rr d0 d0 d n as defined for read page cache (sequential or random) d n 3fh page n page address n micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read page two-plane 00h-00h-30h the read page two-plane (00h-00h-30h) operation is similar to the page read (00h-30h) operation. it transfers two pages of data from the nand flash array to the da- ta registers. each page must be from a different plane on the same die. to enter the read page two-plane mode, write the 00h command to the command register, and then write five address cycles for plane 0 (ba6 = 0). next, write the 00h command to the command register, and five address cycles for plane 1 (ba6 = 1). final- ly, issue the 30h command. the first-plane and second-plane addresses must meet the two-plane addressing requirements, and, in addition, they must have identical column addresses. after the 30h command is written, page data is transferred from both planes to their re- spective data registers in t r. during these transfers, r/b# goes low. when the transfers are complete, r/b# goes high. to read out the data from the plane 0 data register, pulse re# repeatedly. after the data cycle from the plane 0 address completes, issue a random data read two-plane (06h-e0h) command to select the plane 1 address, then repeatedly pulse re# to read out the data from the plane 1 data register. alternatively, the read status (70h) command can monitor data transfers. when the transfers are complete, status register bit 6 is set to 1. to read data from the first of the two planes, the user must first issue the random data read two-plane (06h-e0h) command and pulse re# repeatedly. when the data cycle is complete, issue a random data read two-plane (06h-e0h) command to select the other plane. to output the data beginning at the specified col- umn address, pulse re# repeatedly. use of the read status enhanced (78h) command is prohibited during and follow- ing a page read two-plane operation. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 43: read page two-plane (00h-00h-30h) operation cle we# ale re# i/ox r/b# cle we# ale re# i/ox r/b# 00h col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 00h 30h d out 0 d out 1 d out 06h e0h d out 0 d out 1 d out t r plane 0 address column address j plane 1 address plane 1 address plane 0 data plane 1 data page address m page address m 1 1 column address j micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory read operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
program operations program operations are used to move data from the cache or data registers to the nand array. during a program operation the contents of the cache and/or data registers are modified by the internal control logic. within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (0, 1, 2, .., 63). during a program opera- tion, the contents of the cache and/or data registers are modified by the internal control logic. program operations the program page (80h-10h) command, when not preceded by the program page two-plane (80h-11h) command, programs one page from the cache register to the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that the operation has completed successfully. program cache operations the program page cache (80h-15h) command can be used to improve program op- eration system performance. when this command is issued, the die (lun) goes busy (rdy = 0, ardy = 0) while the cache register contents are copied to the data register, and the die (lun) is busy with a program cache operation (rdy = 1, ardy = 0. while the contents of the data register are moved to the nand flash array, the cache register is available for an additional program page cache (80h-15h) or program page (80h-10h) command. for program page cache series (80h-15h) operations, during the die (lun) busy times, t cbsy and t lprog, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh). when rdy = 1 and ardy = 0, the only valid commands during program page cache series (80h-15h) operations are status op- erations (70h, 78h), program page cache (80h-15h), program page (80h-10h), random data input (85h), program for internal data input (85h), and re- set (ffh). two-plane program operations the program page two-plane (80h-11h) command can be used to improve pro- gram operation system performance by enabling multiple pages to be moved from the cache registers to different planes of the nand flash array. this is done by prepending one or more program page two-plane (80h-11h) commands in front of the pro- gram page (80h-10h) command. two-plane program cache operations the program page two-plane (80h-11h) command can be used to improve pro- gram cache operation system performance by enabling multiple pages to be moved from the cache registers to the data registers and, while the pages are being transferred from the data registers to different planes of the nand flash array, free the cache regis- ters to receive data input from the host. this is done by prepending one or more pro- gram page two-plane (80h-11h) commands in front of the program page cache (80h-15h) command. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
program page (80h-10h) the program page (80h-10h) command enables the host to input data to a cache reg- ister, and moves the data from the cache register to the specified block and page ad- dress in the array of the selected die (lun). this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) when it is busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register and move it to the nand array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page two-plane (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. then write n address cycles containing the column address and row address. data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle the random data input (85h) and program for in- ternal data input (85h) commands may be issued. when data input is complete, write 10h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t prog as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) may be used. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) command could cause more than one die (lun) to respond, resulting in bus con- tention. the program page (80h-10h) command is used as the final command of a two-plane program operation. it is preceded by one or more program page two-plane (80h-11h) commands. data is transferred from the cache registers for all of the ad- dressed planes to the nand array. the host should check the status of the operation by using the status operations (70h, 78h). when internal ecc is enabled, the duration of array programming time is t prog_ecc. during t prog_ecc, the internal ecc generates parity bits when error detection is com- plete. figure 44: program page (80h-10h) operation cycle type i/o[7:0] rdy t adl command address address address address address 80h command 10h command 70h c1 c2 r1 r2 r3 d in d in d in d in d0 d1 dn d out status t wb t prog or t prog_ecc program page cache (80h-15h) the program page cache (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the se- lected die (lun). after the data is copied to the data register, the cache register is availa- micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
ble for additional program page cache (80h-15h) or program page (80h-10h) commands. the program page cache (80h-15h) command is accepted by the die (lun) when it is ready (rdy =1, ardy = 1). it is also accepted by the die (lun) when busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register to move it to the nand array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page two-plane (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. then write n address cycles containing the column address and row address. data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle the random data input (85h) and program for in- ternal data input (85h) commands may be issued. when data input is complete, write 15h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t cbsy to allow the data register to become available from a pre- vious program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block ad- dress. to determine the progress of t cbsy, the host can monitor the target's r/b# signal or, al- ternatively, the status operations (70h, 78h) can be used. when the luns status shows that it is busy with a program cache operation (rdy = 1, ardy = 0), the host should check the status of the failc bit to see if a previous cache operation was successful. if, after t cbsy, the host wants to wait for the program cache operation to complete, without issuing the program page (80h-10h) command, the host should monitor ar- dy until it is 1. the host should then check the status of the fail and failc bits. in devices with more than one die (lun) per target, during and following interleaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) com- mand could cause more than one die (lun) to respond, resulting in bus contention. the program page cache (80h-15h) command is used as the final command of a two-plane program cache operation. it is preceded by one or more program page two-plane (80h-11h) commands. data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the nand flash array. the host should check the status of the operation by using the status opera- tions (70h, 78h). micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 45: program page cache (80hC15h) operation (start) cycle type i/o[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type i/o[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy figure 46: program page cache (80hC15h) operation (end) cycle type i/o[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type rdy t adl command address as defined for page cache program address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 10h 1 t wb t lprog i/o[7:0] micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
program page two-plane (80h-11h) the program page two-plane (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the nand flash array. this command can be issued one or more times. each time a new plane address is specified that plane is also queued for data transfer. to in- put data for the final plane and to begin the program operation for all previously queued planes, issue either the program page (80h-10h) command or the program page cache (80h-15h) command. all of the queued planes will move the data to the nand flash array. this command is accepted by the die (lun) when it is ready (rdy = 1). to input a page to the cache register and queue it to be moved to the nand flash array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page two-plane (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. write five address cycles containing the column address and row ad- dress; data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle, the random data input (85h) and program for internal data input (85h) commands can be issued. when data input is complete, write 11h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. when the lun's status shows that it is ready (rdy = 1), additional program page two-plane (80h-11h) commands can be issued to queue additional planes for data transfer. alternatively, the program page (80h-10h) or program page cache (80h-15h) commands can be is- sued. when the program page (80h-10h) command is used as the final command of a two- plane program operation, data is transferred from the cache registers to the nand flash array for all of the addressed planes during t prog. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit for each of the planes to verify that programming completed successfully. when the program page cache (80h-15h) command is used as the final command of a program cache two-plane operation, data is transferred from the cache registers to the data registers after the previous array operations finish. the data is then moved from the data registers to the nand flash array for all of the addressed planes. this oc- curs during t cbsy. after t cbsy, the host should check the status of the failc bit for each of the planes from the previous program cache operation, if any, to verify that pro- gramming completed successfully. for the program page two-plane (80h-11h), program page (80h-10h), and pro- gram page cache (80h-15h) commands, see two-plane operations for two-plane ad- dressing requirements. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 47: program page two-plane (80hC11h) operation cycle type i/o[7:0] rdy t adl command address address address address address 80h c1 command address 80h ... c2 r1 r2 r3 d in d in d in command d0 dn 11h t wb t dbsy micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory program operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
erase operations erase operations are used to clear the contents of a block in the nand flash array to prepare its pages for program operations. erase operations the erase block (60h-d0h) command, when not preceded by the erase block two-plane (60h-d1h) command, erases one block in the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. two-plane erase operations the erase block two-plane (60h-d1h) command can be used to further system performance of erase operations by allowing more than one block to be erased in the nand array. this is done by prepending one or more erase block two-plane (60h- d1h) commands in front of the erase block (60h-d0h) command. see two-plane operations for details. erase block (60h-d0h) the erase block (60h-d0h) command erases the specified block in the nand flash array. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to erase a block, write 60h to the command register. then write three address cycles containing the row address; the page address is ignored. conclude by writing d0h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t bers while the block is erased. to determine the progress of an erase operation, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78h) can be used. when the die (lun) is ready (rdy = 1, ardy = 1) the host should check the status of the fail bit. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) command could cause more than one die (lun) to respond, resulting in bus con- tention. the erase block (60h-d0h) command is used as the final command of an erase two- plane operation. it is preceded by one or more erase block two-plane (60h-d1h) commands. all blocks in the addressed planes are erased. the host should check the status of the operation by using the status operations (70h, 78h). see two-plane opera- tions for two-plane addressing requirements. figure 48: erase block (60h-d0h) operation cycle type i/o[7:0] rdy command address address address command t wb t bers 60h r1 r2 r3 d0h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory erase operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
erase block two-plane (60h-d1h) the erase block two-plane (60h-d1h) command queues a block in the specified plane to be erased in the nand flash array. this command can be issued one or more times. each time a new plane address is specified, that plane is also queued for a block to be erased. to specify the final block to be erased and to begin the erase operation for all previously queued planes, issue the erase block (60h-d0h) command. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to queue a block to be erased, write 60h to the command register, then write three ad- dress cycles containing the row address; the page address is ignored. conclude by writ- ing d1h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78h) can be used. when the lun's status shows that it is ready (rdy = 1, ardy = 1), additional erase block two-plane (60h- d1h) commands can be issued to queue additional planes for erase. alternatively, the erase block (60h-d0h) command can be issued to erase all of the queued blocks. for two-plane addressing requirements for the erase block two-plane (60h-d1h) and erase block (60h-d0h) commands, see two-plane operations. figure 49: erase block two-plane (60hCd1h) operation cycle type i/o[7:0] rdy command address address address 60h command d1h r1 command address 60h ... r2 r3 t wb t dbsy micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory erase operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
internal data move operations internal data move operations make it possible to transfer data within a device from one page to another using the cache register. this is particularly useful for block man- agement and wear leveling. the internal data move operation is a two-step process consisting of a read for internal data move (00h-35h) and a program for internal data move (85h-10h) command. to move data from one page to another on the same plane, first issue the read for internal data move (00h-35h) command. when the die (lun) is ready (rdy = 1, ardy = 1), the host can transfer the data to a new page by issuing the program for internal data move (85h-10h) command. when the die (lun) is again ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. to prevent bit errors from accumulating over multiple internal data move opera- tions, it is recommended that the host read the data out of the cache register after the read for internal data move (00h-35h) completes and prior to issuing the pro- gram for internal data move (85h-10h) command. the random data read (05h-e0h) command can be used to change the column address. the host should check the data for ecc errors and correct them. when the program for internal data move (85h-10h) command is issued, any corrected data can be input. the program for internal data input (85h) command can be used to change the column ad- dress. it is not possible to use the read for internal data move operation to move data from one plane to another or from one die (lun) to another. instead, use a read page (00h-30h) or read for internal data move (00h-35h) command to read the data out of the nand, and then use a program page (80h-10h) command with data input to program the data to a new plane or die (lun). between the read for internal data move (00h-35h) and program for inter- nal data move (85h-10h) commands, the following commands are supported: status operations (70h, 78h) and column address operations (05h-e0h, 06h-e0h, 85h). the re- set operation (ffh) can be issued after read for internal data move (00h-35h), but the contents of the cache registers on the target are not valid. in devices that have more than one die (lun) per target, once the read for inter- nal data move (00h-35h) is issued, interleaved die (multi-lun) operations are pro- hibited until after the program for internal data move (85h-10h) command is issued. two-plane read for internal data move operations two-plane internal data move read operations improve read data throughput by copy- ing data simultaneously from more than one plane to the specified cache registers. this is done by issuing the read page two-plane (00h-00h-30h) command or the read for internal data move (00h-00h-35h) command. the internal data move program two-plane (85h-11h) command can be used to further system performance of program for internal data move operations by enabling movement of multiple pages from the cache registers to different planes of the nand flash array. this is done by prepending one or more program for inter- nal data move (85h-11h) commands in front of the program for internal da- ta move (85h-10h) command. see two-plane operations for details. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal data move operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read for internal data move (00h-35h) the read for internal data move (00h-35h) command is functionally identical to the read page (00h-30h) command, except that 35h is written to the command regis- ter instead of 30h. though it is not required, it is recommended that the host read the data out of the de- vice to verify the data prior to issuing the program for internal data move (85h-10h) command to prevent the propagation of data errors. if internal ecc is enabled, the data does not need to be toggled out by the host to be corrected and moving data can then be written to a new page without data reloading, which improves system performance. figure 50: read for internal data move (00h-35h) operation cycle type i/o[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h d out d n d out d n+1 d out d n+2 figure 51: read for internal data move (00hC35h) with random data read (05hCe0h) cycle type i/o[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h 1 cycle type i/o[7:0] rdy command address address command t whr 05h c1 c2 e0h d0 dk dj + n dk + 1 dk + 2 1 d out d out d out d out d out d out micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal data move operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 52: internal data move (85h-10h) with internal ecc enabled i/o[7:0] r/b# t r_ecc t prog_ecc 00h 35h address (5 cycles) address (5 cycles) 00h 85h 10h 70h d out status source address destination address 70h status sr bit 0 = 0 read successful sr bit 1 = 0 read error sr bit 0 = 0 read successful sr bit 1 = 0 read error 00h d out is optional figure 53: internal data move (85h-10h) with random data input with internal ecc enabled i/o[7:0] r/b# t r_ecc t prog_ecc 00h 35h address (5 cycles) address (5 cycles) 00h 85h data 70h 70h d out status source address column address 1, 2 (unlimitted repetitions are possible) destination address address (2 cycles) 85h 10h data sr bit 0 = 0 read successful sr bit 1 = 0 read error d out is optional program for internal data move (85hC10h) the program for internal data move (85h-10h) command is functionally iden- tical to the program page (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. figure 54: program for internal data move (85hC10h) operation cycle type i/o[7:0] rdy command address address address address address command t wb t prog 85h c1 c2 r1 r2 r3 10h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal data move operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 55: program for internal data move (85h-10h) with random data input (85h) cycle type i/o[7:0] rdy command address address address address address t wb t prog 85h c1 c2 r1 r2 r3 1 cycle type i/o[7:0] rdy command address address t whr t whr 85h command 10h c1 c2 d in di dj d in d in di + 1 d in dj + 1 d in dj + 2 1 program for internal data move two-plane (85h-11h) the program for internal data move two-plane (85h-11h) command is func- tionally identical to the program page two-plane (85h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. see program operations for further details. figure 56: program for internal data move two-plane (85h-11h) operation cycle type i/o[7:0] rdy t adl command address address address address address 85h c1 command address 85h ... c2 r1 r2 r3 d in d in d in command d0 dn 11h t wb t dbsy micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal data move operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
block lock feature the block lock feature protects either the entire device or ranges of blocks from being programmed and erased. using the block lock feature is preferable to using wp# to pre- vent program and erase operations. block lock is enabled and disabled at power-on through the lock pin. at power-on, if lock is low, all block lock commands are disabled. however if lock is high at power-on, the block lock commands are enabled and, by default, all the blocks on the device are protected, or locked, from program and erase operations, even if wp# is high. before the contents of the device can be modified, the device must first be unlocked. either a range of blocks or the entire device may be unlocked. program and erase operations complete successfully only in the block ranges that have been unlocked. blocks, once unlocked, can be locked again to protect them from further program and erase operations. blocks that are locked can be protected further, or locked tight. when locked tight, the devices blocks can no longer be locked or unlocked until the device is power cycled. wp# and block lock the following is true when the block lock feature is enabled: ? holding wp# low locks all blocks, provided the blocks are not locked tight. ? if wp# is held low to lock blocks, then returned to high, a new unlock command must be issued to unlock blocks. unlock (23h-24h) by default at power-on, if lock is high, all the blocks are locked and protected from program and erase operations. the unlock (23h) command is used to unlock a range of blocks. unlocked blocks have no protection and can be programmed or erased. the unlock command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. when the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. when the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary ad- dress registers are unlocked. the lower boundary block address must be less than the upper boundary block address. the figures below show examples of how the lower and upper boundary address registers work with the invert area bit. to unlock a range of blocks, issue the unlock (23h) command followed by the appro- priate address cycles that indicate the lower boundary block address. then issue the 24h command followed by the appropriate address cycles that indicate the upper boun- dary block address. the least significant page address bit, pa0, should be set to 1 if set- ting the invert area bit; otherwise, it should be 0. the other page address bits should be 0. only one range of blocks can be specified in the lower and upper boundary block ad- dress registers. if after unlocking a range of blocks the unlock command is again is- sued, the new block address range determines which blocks are unlocked. the previous unlocked block address range is not retained. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 57: flash array protected: invert area bit = 0 block 4095 block 4094 block 4093 block 4092 block 4091 block 4090 block 4089 block 4088 block 4087 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 ffch ff8h unprotected area protected area protected area upper block boundary lower block boundary figure 58: flash array protected: invert area bit = 1 ffch ff8h protected area upper block boundary lower block boundary unprotected area unprotected area block 4095 block 4094 block 4093 block 4092 block 4091 block 4090 block 4089 block 4088 block 4087 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 19: block lock address cycle assignments ale cycle i/o[15:8] 1 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ba7 ba6 low low low low low invert area bit 2 second low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 third low low low low low low low ba17 ba16 notes: 1. i/o[15:8] is applicable only for x16 devices. 2. invert area bit is applicable for 24h command; it may be low or high for 23h com- mand. figure 59: unlock operation unlock lower boundary upper boundary cle ce# we# ale re# wp# i/ox r/b# 23h 24h block add 1 block add 2 block add 3 block add 1 block add 2 block add 3 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
lock (2ah) by default at power-on, if lock is high, all the blocks are locked and protected from program and erase operations. if portions of the device are unlocked using the un- lock (23h) command, they can be locked again using the lock (2ah) command. the lock command locks all of the blocks in the device. locked blocks are write-protected from program and erase operations. to lock all of the blocks in the device, issue the lock (2ah) command. when a program or erase operation is issued to a locked block, r/b# goes low for t lbsy. the program or erase operation does not complete. any read status com- mand reports bit 7 as 0, indicating that the block is protected. the lock (2ah) command is disabled if lock is low at power-on or if the device is locked tight. figure 60: lock operation lock command cle ce# we# i/ox 2ah micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
lock tight (2ch) the lock tight (2ch) command prevents locked blocks from being unlocked and al- so prevents unlocked blocks from being locked. when this command is issued, the un- lock (23h) and lock (2ah) commands are disabled. this provides an additional level of protection against inadvertent program and erase operations to locked blocks. to implement lock tight in all of the locked blocks in the device, verify that wp# is high and then issue the lock tight (2ch) command. when a program or erase operation is issued to a locked block that has also been locked tight, r/b# goes low for t lbsy. the program or erase operation does not complete. the read status (70h) command reports bit 7 as 0, indicating that the block is protected. program and erase operations complete successfully to blocks that were not locked at the time the lock tight command was issued. after the lock tight command is issued, the command cannot be disabled via a soft- ware command. the only ways to disable the lock tight status is to power cycle the de- vice. when the lock tight status is disabled, all of the blocks become locked, the same as if the lock (2ah) command had been issued. the lock tight (2ch) command is disabled if lock is low at power-on. figure 61: lock tight operation lock tight command lock wp# cle ce# we# i/ox r/b# 2ch micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 62: program/erase issued to locked block r/b# i/ox program or erase add ress/data input confirm 70h 60h t lbsy locked block read status block lock read status (7ah) the block lock read status (7ah) command is used to determine the protection status of individual blocks. the address cycles have the same format, as shown below, and the invert area bit should be set low. on the falling edge of re# the i/o pins output the block lock status register, which contains the information on the protection status of the block. table 20: block lock status register bit definitions block lock status register definitions i/o[7:3] i/o2 (lock#) i/o1 (lt#) i/o0 (lt) block is locked tight x 0 0 1 block is locked x 0 1 0 block is unlocked, and device is locked tight x 1 0 1 block is unlocked, and device is not locked tight x 1 1 0 figure 63: block lock read status block lock read status block address cle ce# we# ale re# i/ox 7ah add 1 add 2 add 3 status t whr micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 64: block lock flowchart power-up power-up with lock high lock tight cmd with wp# and lock high lock tight cmd with wp# and lock high lock tight cmd with wp# and lock high unlock cmd with invert area bit = 1 wp# low >100ns or lock cmd wp# low >100ns or lock cmd unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 0 entire nand flash array locked entire nand flash array locked tight block lock function disabled unlocked range locked range unlocked range unlocked range locked tight range unlocked range locked tight range unlocked range locked-tight range power-up with lock low (default) locked range unlocked range locked range micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory block lock feature pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
one-time programmable (otp) operations this micron nand flash device offers a protected, one-time programmable nand flash memory area. thirty full pages (2112 bytes per page) of otp data are available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. customers can use the otp area any way they choose; typical uses include programming serial numbers or other data for permanent storage. the otp area leaves the factory in an unwritten state (all bits are 1s). programming or partial-page programming enables the user to program only 0 bits in the otp area. the otp area cannot be erased, whether it is protected or not. protecting the otp area pre- vents further programming of that area. micron provides a unique way to program and verify data before permanently protect- ing it and preventing future changes. the otp area is only accessible while in otp oper- ation mode. to set the device to otp operation mode, issue the set feature (efh) command to feature address 90h and write 01h to p1, followed by three cycles of 00h to p2-p4. for parameters to enter otp mode, see features operations. when the device is in otp operation mode, all subsequent page read (00h-30h) and program page (80h-10h) commands are applied to the otp area. the otp area is as- signed to page addresses 02h-1fh. to program an otp page, issue the program page (80h-10h) command. the pages must be programmed in the ascending order. similarly, to read an otp page, issue the page read (00h-30h) command. protecting the otp is done by entering otp protect mode. to set the device to otp pro- tect mode, issue the set feature (efh) command to feature address 90h and write 03h to p1, followed by three cycles of 00h to p2-p4. to determine whether the device is busy during an otp operation, either monitor r/b# or use the read status (70h) command. to exit otp operation or protect mode, write 00h to p1 at feature address 90h. legacy otp commands for legacy otp commands, otp data program (a0h-10h), otp data protect (a5h-10h), and otp data read (afh-30h), refer to the mt29f4gxxaxc data sheet. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
otp data program (80h-10h) the otp data program (80h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or a page can be partially programmed up to eight times. only the otp area allows up to eight partial-page pro- grams. the rest of the blocks support only four partial-page programs. there is no erase operation for otp pages. program page enables programming into an offset of an otp page using two bytes of the column address (ca[12:0]). the command is compatible with the random data input (85h) command. the program page command will not execute if the otp area has been protected. to use the program page command, issue the 80h command. issue n address cycles. the first two address cycles are the column address. for the remaining cycles, select a page in the range of 02h-00h through 1fh-00h. next, write from 1C2112 bytes of data. after data input is complete, issue the 10h command. the internal control logic auto- matically executes the proper programming algorithm and controls the necessary tim- ing for programming and verification. r/b# goes low for the duration of the array programming time ( t prog). the read status (70h) command is the only valid command for reading status in otp operation mode. bit 5 of the status register reflects the state of r/b#. when the device is ready, read bit 0 of the status register to determine whether the operation passed or failed (see status operations). each otp page can be programmed to 8 partial-page programming. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
random data input (85h) after the initial otp data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input command can be used any number of times in the same page prior to the otp page write (10h) command being issued. figure 65: otp data program (after entering otp operation mode) we# ce# ale cle re# r/b# i/ox dont care otp data written (following good status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2112 bytes x16 device: m = 1056 words 80h col add 1 col add 2 d in n d in m 00h 00h 10h 70h status otp page 1 otp address 1 note: 1. the otp page must be within the 02hC1fh range. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 66: otp data program operation with random data input (after entering otp opera- tion mode) we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add1 col add2 otp page 1 d in n+1 t adl t adl random data input command column address program command read status command serial input 85h col add1 70h status 10h t prog t wb dont care 00h 00h d in n col add2 d in n d in n+1 otp data protect (80h-10) the otp data protect (80h-10h) command is used to prevent further programming of the pages in the otp area. to protect the otp area, the target must be in otp opera- tion mode. to protect all data in the otp area, issue the 80h command. issue n address cycles in- cluding the column address, otp protect page address and block address; the column and block addresses are fixed to 0. next, write 00h data for the first byte location and issue the 10h command. r/b# goes low for the duration of the array programming time, t prog. after the data is protected, it cannot be programmed further. when the otp area is pro- tected, the pages within the area are no longer programmable and cannot be unprotec- ted. the read status (70h) command is the only valid command for reading status in otp operation mode. the rdy bit of the status register will reflect the state of r/b#. use of the read status enhanced (78h) command is prohibited. when the target is ready, read the fail bit of the status register to determine if the oper- ation passed or failed. if the otp data protect (80h-10h) command is issued after the otp area has already been protected, r/b# goes low for t obsy. after t obsy, the status register is set to 60h. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 67: otp data protect operation (after entering otp protect mode) we# ce# ale cle re# r/b# i/ox dont care t wc t wb t prog otp data protect command otp address otp data protected 1 program command read status command 80h col 00h col 00h 10h 70h status otp page 00h 00h d in note: 1. otp data is protected following a good status confirmation. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
otp data read (00h-30h) to read data from the otp area, set the device to otp operation mode, then issue the page read (00h-30h) command. data can be read from otp pages within the otp area whether the area is protected or not. to use the page read command for reading data from the otp area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column ad- dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1fh-00h-00h. lastly, issue the 30h command. the page read cache mode command is not supported on otp pages. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command is the only valid command for reading status in otp op- eration mode. bit 5 of the status register reflects the state of r/b# (see status opera- tions). normal read operation timings apply to otp read accesses. additional pages within the otp area can be selected by repeating the otp data read command. the page read command is compatible with the random data output (05h-e0h) command. only data on the current page can be read. pulsing re# outputs data sequentially. figure 68: otp data read we# ce# ale cle re# r/b# i/ox busy t r 00h 00h 00h 30h col add 1 col add 2 dont care otp page 1 otp address d out n d out n + 1 d out m note: 1. the otp page must be within the 02hC1fh range. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 69: otp data read with random data read operation we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 otp page 1 00h 00h 00h t r t ar t rr dont care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t whr t clr d out n d out n + 1 30h t wb column address n column address m note: 1. the otp page must be within the range 02hC1fh. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory one-time programmable (otp) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
two-plane operations each nand flash logical unit (lun) is divided into multiple physical planes. each plane contains a cache register and a data register independent of the other planes. the planes are addressed via the low-order block address bits. specific details are provided in device and array organization. two-plane operations make better use of the nand flash arrays on these physical planes by performing concurrent read, program, or erase operations on multiple planes, significantly improving system performance. two-plane operations must be of the same type across the planes; for example, it is not possible to perform a program operation on one plane with an erase operation on another. when issuing two-plane program or erase operations, use the read status (70h) command and check whether the previous operation(s) failed. if the read status (70h) command indicates that an error occurred (fail = 1 and/or failc = 1), use the read status enhanced (78h) command to determine which plane operation failed. two-plane addressing two-plane commands require multiple, five-cycle addresses, one address per opera- tional plane. for a given two-plane operation, these addresses are subject to the follow- ing requirements: ? the lun address bit(s) must be identical for all of the issued addresses. ? the plane select bit, ba[6], must be different for each issued address. ? the page address bits, pa[5:0], must be identical for each issued address. the read status (70h) command should be used following two-plane program page and erase block operations on a single die (lun). micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 70: two-plane page read cle we# ale re# i/ox r/b# cle we# ale re# i/ox r/b# 00h col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 00h 30h d out 0 d out 1 d out 06h e0h d out 0 d out 1 d out t r plane 0 address column address j plane 1 address plane 1 address plane 0 data plane 1 data page address m page address m 1 1 column address j notes: 1. column and page addresses must be the same. 2. the least significant block address bit, ba6, must be different for the first- and second- plane addresses. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 71: two-plane page read with random data read r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 05h e0h 30h t r plane 0 address plane 0 data plane 0 data address (5 cycles) address (2 cycles) data output data output plane 1 address 06h 05h e0h e0h plane 1 data plane 1 data address (5 cycles) address (2 cycles) data output data output plane 1 address 1 1 figure 72: two-plane program page r/b# i/ox 80h address (5 cycles) 70h 10h 11h 80h t dbsy t prog 1st-plane address address (5 cycles) data input data input status 2nd-plane address micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 73: two-plane program page with random data input r/b# i/ox r/b# i/ox 80h address (5 cycles) 11h 80h 85h t dbsy t prog 1st-plane address address (2 cycles) data input address (5 cycles) 2nd-plane address data input data input 85h 10h address (2 cycles) 1 1 data input different column address than previous 5 address cycles, for 1st plane only different column address than previous 5 address cycles, for 2nd plane only unlimited number of repetitions unlimited number of repetitions micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 74: two-plane program page cache mode r/b# i/ox 80h address/data input 11h 80h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 1 1 2 r/b# i/ox 80h address/data input 11h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 2 r/b# i/ox 80h address/data input 11h 10h t dbsy t lprog 1st plane 2nd plane address/data input 80h 80h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 75: two-plane internal data move r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 85h 11h address (5 cycles) 1st-plane destination address (5 cycles) 2nd-plane source 1 r/b# i/ox 85h 10h address (5 cycles) t prog 2nd-plane destination 70h status 1 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 76: two-plane internal data move with two-plane random data read r/b# re# i/ox r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 35h t r 1st-plane source data output data from 1st-plane source address (5 cycles) 2nd-plane source e0h address (2 cycles) 06h e0h address (5 cycles) 2nd-plane source address data from 2nd-plane source 2nd-plane source column address 05h data output 11h t dbsy data output data from 2nd-plane source from new column address 85h 85h 10h address (5 cycles) 2nd-plane destination address (5 cycles) 1st-plane destination 2 2 t prog 70h status 1 1 optional micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 77: two-plane internal data move with random data input r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 1st-plane destination 2nd-plane destination 85h data data address (5 cycles) optional 85h 11h address (2 cycles) unlimited number of repetitions address (5 cycles) 2nd-plane source 1 r/b# i/ox t prog 85h data data address (5 cycles) optional 85h 10h 70h status address (2 cycles) unlimited number of repetitions 1 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 78: two-plane block erase re# ce# ale cle i/ox r/b# we# t dbsy status 70h or 78h t bers 1st plane 2nd plane optional dont care address input (3 cycles) d0h 60h d1h address input (3 cycles) 60h figure 79: two-plane/multiple-die read status cycle 78h address (3 cycles) status output t whr t ar t rea ce# cle we# ale re# i/ox micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory two-plane operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
interleaved die (multi-lun) operations in devices that have more than one die (lun) per target, it is possible to improve per- formance by interleaving operations between the die (luns). an interleaved die (multi- lun) operation is one that is issued to an idle die (lun) (rdy = 1) while another die (lun) is busy (rdy = 0). interleaved die (multi-lun) operations are prohibited following reset (ffh), identifi- cation (90h, ech, edh), and configuration (eeh, efh) operations until ardy =1 for all of the die (luns) on the target. during an interleaved die (multi-lun) operation, there are two methods to determine operation completion. the r/b# signal indicates when all of the die (luns) have finish- ed their operations. r/b# remains low while any die (lun) is busy. when r/b# goes high, all of the die (luns) are idle and the operations are complete. alternatively, the read status enhanced (78h) command can report the status of each die (lun) in- dividually. if a die (lun) is performing a cache operation, like program page cache (80h-15h), then the die (lun) is able to accept the data for another cache operation when status register bit 6 is 1. all operations, including cache operations, are complete on a die when status register bit 5 is 1. during and following interleaved die (multi-lun) operations, the read status (70h) command is prohibited. instead, use the read status enhanced (78h) command to monitor status. this command selects which die (lun) will report status. when two- plane commands are used with interleaved die (multi-lun) operations, the two-plane commands must also meet the requirements in two-plane operations. see command definitions for the list of commands that can be issued while other die (luns) are busy. during an interleaved die (multi-lun) operation that involves a program series (80h-10h, 80h-15h) operation and a read operation, the program series operation must be issued before the read series operation. the data from the read series opera- tion must be output to the host before the next program series operation is issued. this is because the 80h command clears the cache register contents of all cache regis- ters on all planes. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory interleaved die (multi-lun) operations pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
error management each nand flash die (lun) is specified to have a minimum number of valid blocks (nvb) of the total available blocks. this means the die (luns) could have blocks that are invalid when shipped from the factory. an invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ecc. additional blocks can develop with use. however, the total number of available blocks per die (lun) will not fall below nvb during the endurance life of the product. although nand flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad block management and error-correction algo- rithms. this type of software environment ensures data integrity. internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to program the bad block mark into every loca- tion in the first page of each invalid block. it may not be possible to program every loca- tion with the bad block mark. however, the first spare area location in each bad block is guaranteed to contain the bad block mark. this method is compliant with onfi factory defect mapping requirements. see the following table for the first spare area location and the bad block mark. system software should check the first spare area location on the first page of each block prior to performing any program or erase operations on the nand flash de- vice. a bad block table can then be created, enabling system software to map around these areas. factory testing is performed under worst-case conditions. because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? always check status after a program or erase operation ? under typical conditions, use the minimum required ecc (see table below) ? use bad block management and wear-leveling algorithms the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. table 21: error management details description requirement minimum number of valid blocks (nvb) per lun 4016 total available blocks per lun 4096 first spare area location x8: byte 2048 x16: word 1024 bad-block mark x8: 00h x16: 0000h minimum required ecc 4-bit ecc per 528 bytes micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory error management pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 21: error management details (continued) description requirement minimum ecc with internal ecc enabled 4-bit ecc per 516 bytes (user data) + 8 bytes (parity data) minimum required ecc for block 0 if program/ erase cycles are less than 1000 1-bit ecc per 528 bytes micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory error management pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
internal ecc and spare area mapping for ecc internal ecc enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata i in the spare area. the metadata ii area, which consists of two bytes (x8) and one word (x16), is not ecc protected. during the busy time for program operations, internal ecc generates parity bits when error detection is complete. during read operations the device executes the internal ecc engine (5-bit detection and 4-bit error correction). when the read operaton is complete, read status bit 0 must be checked to determine whether errors larger than four bits have occurred. following the read status command, the device must be returned to read mode by issuing the 00h command. limitations of internal ecc include the spare area, defined in the figures below, and ecc parity areas that cannot be written to. each ecc user area (referred to as main and spare) must be written within one partial-page program so that the nand device can calculate the proper ecc parity. the number of partial-page programs within a page cannot exceed four. figure 80: spare area mapping (x8) max byte min byte ecc protected area description address address 1ffh 000h y es main 0 user data 3ffh 200h y es main 1 user data 5ffh 400h y es main 2 user data 7ffh 600h y es main 3 user data 801h 800h no reserved 803h 802h no user metadata ii 807h 804h y es spare 0 user metadata i 80fh 808h y es spare 0 ecc for main/spare 0 811h 810h no reserved 813h 812h no user metadata ii 817h 814h y es spare 1 user metadata i 81fh 818h y es spare 1 ecc for main/spare 1 821h 820h no reserved 823h 822h no user metadata ii 827h 824h y es spare 2 user metadata i 82fh 828h y es spare 2 ecc for main/spare 2 831h 830h no user data 833h 832h no user metadata ii 837h 834h y es spare 3 user metadata i 83fh 838h y es spare 3 ecc for main/spare 3 bad block ecc user data information parity (metadata) 2 bytes 8 bytes 6 bytes micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal ecc and spare area mapping for ecc pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 81: spare area mapping (x16) max word min word ecc protected area description address address 0ffh 000h y es main 0 user data 1ffh 100h y es main 1 user data 2ffh 200h y es main 2 user data 3ffh 300h y es main 3 user data 400h 400h no reserved 401h 401h no user metadata ii 403h 402h y es spare 0 user metadata i 407h 404h y es spare 0 ecc for main/spare 0 408h 408h no reserved 409h 409h no user metadata ii 40bh 40ah y es spare 1 user metadata i 40fh 40ch y es spare 1 ecc for main/spare 1 410h 410h no reserved 411h 411h no user metadata ii 413h 412h y es spare 2 user metadata i 417h 414h y es spare 2 ecc for main/spare 2 418h 418h no user data 419h 419h no user metadata ii 41bh 41ah y es spare 3 user metadata i 41fh 41ch y es spare 3 ecc for main/spare 3 bad block ecc user data information parity (metadata) 1 word 4 words 3 words micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory internal ecc and spare area mapping for ecc pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed can cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not guar- anteed. exposure to absolute maximum rating conditions for extended periods can af- fect reliability. table 22: absolute maximum ratings voltage on any pin relative to vss parameter/condition symbol min max unit voltage input 1.8v v in C0.6 2.4 v 3.3v C0.6 4.6 v v cc supply voltage 1.8v v cc C0.6 2.4 v 3.3v C0.6 4.6 v storage temperature t stg C65 150 c short circuit output current, i/os C C 5 ma table 23: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0 C 70 c industrial C40 C 85 c v cc supply voltage 1.8v v cc 1.7 1.8 1.95 v 3.3v 2.7 3.3 3.6 v ground supply voltage v ss 0 0 0 v table 24: valid blocks parameter symbol device min max unit notes valid block number nvb mt29f4g 4016 4096 blocks 1, 2 mt29f8g 8032 8192 blocks 1, 2, 3 notes: 1. invalid blocks are blocks that contain one or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below nvb during the endurance life of the device. do not erase or program blocks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid with ecc when shipped from the factory. 3. each 4gb section has a maximum of 80 invalid blocks. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 25: capacitance notes 1C3 apply to all parameters and conditions description symbol max unit input capacitance c in 10 pf input/output capacitance (i/o) c io 10 pf notes: 1. these parameters are verified in device characterization and are not 100% tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. 3. capacitance (c in = c io = 20pf) for mt29f8g and (c in = c io = 40pf) for mt29f16g. table 26: test conditions parameter value notes input pulse levels 0.0v to v cc input rise and fall times 1.8v 2.5ns 3.3v 5.0ns input and output timing levels v cc /2 output load 1 ttl gate and cl = 30pf (1.8v) 1 1 ttl gate and cl = 50pf (3.3v) output load 1 ttl gate and cl = 30pf (1.8v) 1 1 ttl gate and cl = 50pf (3.3v) note: 1. verified in device characterization, not 100% tested. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications C dc characteristics and operating conditions table 27: dc characteristics and operating conditions (3.3v) parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc1 C 25 35 ma program current C i cc2 C 25 35 ma erase current C i cc3 C 25 35 ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb1 C C 1 ma standby current (cmos) ce# = v cc - 0.2v; wp# = 0v/v cc i sb2 C 20 100 a staggered power-up cur- rent rise time = 1ms line capacitance = 0.1f i st C C 10 per die ma 1 input leakage current v in = 0v to v cc i li C C 10 a output leakage current v out = 0v to v cc i lo C C 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp# v ih 0.8 x v cc C v cc + 0.3 v input low voltage, all in- puts C v il C0.3 C 0.2 x v cc v output high voltage i oh = C400a v oh 0.67 x v cc C C v 3 output low voltage i ol = 2.1ma v ol C C 0.4 v 3 output low current v ol = 0.4v i ol (r/b#) 8 10 C ma 2 notes: 1. measurement is taken with 1ms averaging intervals and begins after v cc reaches v cc (min). 2. i ol (r/b#) may need to be relaxed if r/b pull-down strength is not set to full. 3. v oh and v ol may need to be relaxed if i/o drive strength is not set to full. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C dc characteristics and operating conditions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 28: dc characteristics and operating conditions (1.8v) parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc1 C 13 20 ma 1, 2 program current C i cc2 C 10 20 ma 1, 2 erase current C i cc3 C 10 20 ma 1, 2 standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb1 C C 1 ma standby current (cmos) ce# = v cc - 0.2v; wp# = 0v/v cc i sb2 C 10 50 a staggered power-up cur- rent rise time = 1ms line capacitance = 0.1f i st C C 10 per die ma 3 input leakage current v in = 0v to v cc i li C C 10 a output leakage current v out = 0v to v cc i lo C C 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp# v ih 0.8 x v cc C v cc + 0.3 v input low voltage, all in- puts C v il C0.3 C 0.2 x v cc v output high voltage i oh = C100a v oh v cc - 0.1 C C v 4 output low voltage i ol = +100a v ol C C 0.1 v 4 output low current (r/b#) v ol = 0.2v i ol (r/b#) 3 4 C ma 5 notes: 1. typical and maximum values are for single-plane operation only. if device supports dual- plane operation, values are 20ma (typ) and 40ma (max). 2. values are for single-die operations. values could be higher for interleaved-die opera- tions. 3. measurement is taken with 1ms averaging intervals and begins after v cc reaches v cc (min). 4. test conditions for v oh and v ol . 5. dc characteristics may need to be relaxed if r/b# pull-down strength is not set to full. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C dc characteristics and operating conditions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications C ac characteristics and operating conditions table 29: ac characteristics: command, data, and address input (3.3v) note 1 applies to all parameter symbol min max unit notes ale to data start t adl 70 C ns 2 ale hold time t alh 5 C ns ale setup time t als 10 C ns ce# hold time t ch 5 C ns cle hold time t clh 5 C ns cle setup time t cls 10 C ns ce# setup time t cs 15 C ns data hold time t dh 5 C ns data setup time t ds 7 C ns write cycle time t wc 20 C ns 2 we# pulse width high t wh 7 C ns 2 we# pulse width t wp 10 C ns 2 wp# transition to we# low t ww 100 C ns notes: 1. operating mode timings meet onfi timing mode 5 parameters. 2. timing for t adl begins in the address cycle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. table 30: ac characteristics: command, data, and address input (1.8v) note 1 applies to all parameter symbol min max unit notes ale to data start t adl 70 C ns 2 ale hold time t alh 5 C ns ale setup time t als 10 C ns ce# hold time t ch 5 C ns cle hold time t clh 5 C ns cle setup time t cls 10 C ns ce# setup time t cs 20 C ns data hold time t dh 5 C ns data setup time t ds 10 C ns write cycle time t wc 25 C ns 2 we# pulse width high t wh 10 C ns 2 we# pulse width t wp 12 C ns 2 wp# transition to we# low t ww 100 C ns notes: 1. operating mode timings meet onfi timing mode 4 parameters. 2. timing for t adl begins in the address cycle on the final rising edge of we#, and ends with the first rising edge of we# for data input. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 31: ac characteristics: normal operation (3.3v) note 1 applies to all parameter symbol min max unit notes ale to re# delay t ar 10 C ns ce# access time t cea C 25 ns ce# high to output high-z t chz C 50 ns 2 cle to re# delay t clr 10 C ns ce# high to output hold t coh 15 C ns output high-z to re# low t ir 0 C ns read cycle time t rc 20 C ns re# access time t rea C 16 ns re# high hold time t reh 7 C ns re# high to output hold t rhoh 15 C ns re# high to we# low t rhw 100 C ns re# high to output high-z t rhz C 100 ns 2 re# low to output hold t rloh 5 C ns re# pulse width t rp 10 C ns ready to re# low t rr 20 C ns reset time (read/program/erase) t rst C 5/10/500 s 3 we# high to busy t wb C 100 ns we# high to re# low t whr 60 C ns notes: 1. ac characteristics may need to be relaxed if i/o drive strength is not set to full. 2. transition is measured 200mv from steady-state voltage with load. this parameter is sampled and not 100% tested. 3. the first time the reset (ffh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. thereafter, the device goes busy for a maximum of 5s. table 32: ac characteristics: normal operation (1.8v) note 1 applies to all parameter symbol min max unit notes ale to re# delay t ar 10 C ns ce# access time t cea C 25 ns ce# high to output high-z t chz C 50 ns 2 cle to re# delay t clr 10 C ns ce# high to output hold t coh 15 C ns output high-z to re# low t ir 0 C ns read cycle time t rc 25 C ns re# access time t rea C 22 ns re# high hold time t reh 10 C ns re# high to output hold t rhoh 15 C ns re# high to we# low t rhw 100 C ns micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 32: ac characteristics: normal operation (1.8v) (continued) note 1 applies to all parameter symbol min max unit notes re# high to output high-z t rhz C 65 ns 2 re# low to output hold t rloh 3 C ns re# pulse width t rp 12 C ns ready to re# low t rr 20 C ns reset time (read/program/erase) t rst C 5/10/500 s 3 we# high to busy t wb C 100 ns we# high to re# low t whr 80 C ns notes: 1. ac characteristics may need to be relaxed if i/o drive strength is not set to full. 2. transition is measured 200mv from steady-state voltage with load. this parameter is sampled and not 100% tested. 3. the first time the reset (ffh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. thereafter, the device is busy for a maximum of 5s. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications C program/erase characteristics table 33: program/erase characteristics parameter symbol typ max unit notes number of partial-page programs nop C 4 cycles 1 block erase operation time t bers 0.7 3 ms busy time for program cache operation t cbsy 3 600 s 2 cache read busy time t rcbsy 3 25 s busy time for set features and get features operations t feat C 1 s busy time for otp data program operation if otp is pro- tected t obsy C 30 s busy time for program/erase on locked blocks t lbsy C 3 s program page operation time, internal ecc disabled t prog 200 600 s 8 program page operation time, internal ecc enabled t prog_ecc 220 600 s 3, 8 data transfer from flash array to data register, internal ecc disabled t r C 25 s 6, 7 data transfer from flash array to data register, internal ecc enabled t r_ecc 45 70 s 3, 5 busy time for otp data program operation if otp is pro- tected, internal ecc enabled t obsy_ecc C 50 s busy time for two-plane program page or two-plane block erase operation t dbsy 0.5 1 s notes: 1. four total partial-page programs to the same page. if ecc is enabled, then the device is limited to one partial-page program per ecc user area, not exceeding four partial-page programs per page. 2. t cbsy max time depends on timing between internal program completion and data-in. 3. parameters are with internal ecc enabled. 4. typical is nominal voltage and room temperature. 5. typical t r_ecc is under typical process corner, nominal voltage, and at room tempera- ture. 6. data transfer from flash array to data register with internal ecc disabled. 7. ac characteristics may need to be relaxed if i/o drive strength is not set to full. 8. typical program time is defined as the time within which more than 50% of the pages are programmed at nominal voltage and room temperature. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory electrical specifications C program/erase characteristics pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
asynchronous interface timing diagrams figure 82: reset operation cle ce# we# r/b# i/o[7:0] t rst t wb ffh reset command figure 83: read status cycle re# ce# we# cle i/o[7:0] t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output dont care t cea t coh micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 119 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 84: read status enhanced cycle t whr t ar dont care 78h row add 1 row add 2 row add 3 status output t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t cea t chz t rea t rhoh t rhz t coh i/o[7:0] re# ale we# cle ce# figure 85: read parameter page we# ale cle re# r/b# ech 00h t r or t r_ecc p0 0 p1 0 p255 0 p0 1 t wb t rr i/o[7:0] t rp t rc micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 120 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 86: read page d out n d out n + 1 d out m we# ce# ale cle re# rdy i/ox t wc busy 00h 30h t r or t r_ecc t wb t ar t rr t rp t clr t rc t rhz dont care col add 1 col add 2 row add 1 row add 2 row add 3 micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 121 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 87: read page operation with ce# dont care re# ce# t rea t chz t coh t cea re# ce# ale cle i/ox i/ox out rdy we# data output t r or t r_ecc dont care address (5 cycles) 00h 30h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 122 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 88: random data read we# ce# ale cle re# rdy i/ox t rhw t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n - 1 d out n t whr column address m micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 123 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 89: read page cache sequential t wc we# ce# ale cle re# rdy i/ox column address 0 page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh t rr t wb t r t rc t rea 30h dout 0 31h col add 2 row add 1 row add 2 row add 3 00h t rcbsy col add 1 t rhw dout 1 t clh t ch t ds t wb t cls t cs dout 31h 1 we# ce# ale cle re# rdy i/ox column address 0 page address m t rc t rea dout 0 t rhw dout 1 dont care column address 0 t clh t ch t rea t cea t rhw t ds t rr t rcbsy t wb column address 0 dout 0 dout 3fh dout 0 dout t cls t cs t rc dout 31h t rcbsy dout 1 dout 1 page address m + 1 page address m + 2 1 t dh t dh micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 124 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 90: read page cache random t wc we# ce# ale cle re# rdy i/ox page address m column address 00h t ds t clh t cls t cs t ch t dh t wb t r 30h 00h col add 2 row add 1 row add 2 row add 3 00h col add 1 page address n column address 00h col add 2 row add 1 row add 2 col add 1 1 we# ce# ale cle re# rdy i/ox dont care column address 0 t ch t rea t cea trhw t ds t dh t rr t rcbsy t wb column address 0 dout 0 dout 3fh dout 0 dout t cs t rc 31h t rcbsy dout 1 dout 1 page address m page address n page address n column address 00h col add 2 row add 1 row add 2 row add 3 col add 1 1 t clh t cls micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 125 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 91: read id operation we# ce# ale cle re# i/ox address, 1 cycle 90h 00h or 20h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr figure 92: program page operation we# ce# ale cle re# rdy i/ox t wc t adl 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog or t prog_ecc t whr t wb dont care micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 126 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 93: program page operation with ce# dont care address (5 cycles) data input 10h we# ce# t wp t ch t cs dont care data input 80h cle ce# we# ale i/ox figure 94: program page operation with random data input we# ce# ale cle re# rdy i/ox t wc serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in m d in n t adl t adl change write column command column address read status command serial input 85h t prog or t prog_ecc t wb t whr dont care col add 1 col add 2 d in p d in q 70h status 10h micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 127 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 95: program page cache we# ce# ale cle re# rdy i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 din m din n din m din n last page - 1 last page serial input t wc dont care 80h t adl row add 3 figure 96: program page cache ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 din m din n din m din n last page last page C 1 serial input t wc dont care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page C 1 program successful t adl t whr t whr t adl micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 128 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 97: internal data move we# ce# ale cle re# rdy i/ox t wb t prog t wb busy busy read status command t wc dont care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h col add 2 row add 1 row add 2 row add 3 35h (or 30h) col add 1 85h data 1 t r data input optional figure 98: internal data move (85h-10h) with internal ecc enabled i/o[7:0] r/b# t r_ecc t prog_ecc 00h 35h address (5 cycles) address (5 cycles) 00h 85h 10h 70h d out status source address destination address 70h status sr bit 0 = 0 read successful sr bit 1 = 0 read error sr bit 0 = 0 read successful sr bit 1 = 0 read error 00h d out is optional micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 129 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 99: internal data move (85h-10h) with random data input with internal ecc enabled i/o[7:0] r/b# t r_ecc t prog_ecc 00h 35h address (5 cycles) address (5 cycles) 00h 85h data 70h 70h d out status source address column address 1, 2 (unlimitted repetitions are possible) destination address address (2 cycles) 85h 10h data sr bit 0 = 0 read successful sr bit 1 = 0 read error d out is optional figure 100: erase block operation we# ce# ale cle re# rdy i/o[7:0] read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr dont care i/o0 = 0, pass i/o0 = 1, fail micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 130 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
revision history rev. n C 10/12 ? updated part number chart with option x for product longevity program (plp) under special options rev. m C 02/12 ? updated i sb2 spec in 3.3v dc characteristics and operating conditions table rev. l C 1/12 ? updated 63-ball package dimension drawing ? corrected the p1 values in the feature addresses 01h: timing mode table rev. k C 11/11 ? command definitions topic, command set table: changed otp data lock by block (onfi) to otp data lock by page (onfi); fixed unresolved xref to c_inter- leaved_die_multi-lun_operations.dita in note 2 ? one-time programmable (otp) operations topic, otp data protect (80h-10) sec- tion: updated content rev. j C 09/11 ? deleted ocpl notation from 48-pin tsop C type 1 figure ? removed former 48-pin tsop C type 1, cpl figure rev. i C 07/11 ? added 16gb and 16gb part numbers to document ? updated part number chart to include 16gb ? added 16gb density to device and array organization ? clarification to notes for electrical specifications table rev. h C 12/10 ? updated status bit 1 under program page in status operations rev. g C 10/10 ? removed the words "or by factory (always enabled)" from the general description rev. f C 06/10 ? replaced blank with 3 for number of valid address cycles on block erase two-plane in the two-plane command set table rev. e C 05/10 ? changed status to production ? added part numbers to document micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory revision history pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 131 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
? removed endurance spec from features and parameter page data structure table ? filled in missing values to read id table ? changed t bers from .5 to .7 in electrical specifications C program/erase characteris- tics ? replaced status register definition table with the correct one for ecc rev. d C 03/10 ? updated value for byte 113 to 01h; value for byte 114 to 0eh in parameter page data structure tables ? updated note 6 in electrical specifications - program/erase characteristics to say "disabled" ? fixed note typo in features ? updated otp protect - changed to protect by block; removed protect by page ? updated 1.8v active current specs for single die and fixed typos in dc tables rev. c C 01/10 ? updated read id tables to include the following value changes: byte 1 C mt29f4g08abbda (4gb, x8, 1.8v) value: ach, mt29f4g16abbda (4gb, x16, 1.8v) value: bch; byte 2 C mt29f4g08abbda value: 90h, mt29f4g16abbda value: 90h; byte 3 C mt29f4g08abbda value: 15h, mt29f4g16abbda value: 55h; byte 4 C mt29f4g08abbda value: 56h, mt29f4g16abbda value: 56h; removed h4 from part numbers ? added bare die parameter page data structure table ? removed boot block rev. b C 10/09 ? removed part numbers: mt29f4g08abbdawp and mt29f4g16abbdawp ? updated "internal data move with internal ecc enabled" graphic spec from t r to t r_ecc ? updated "internal data move with random data input with internal ecc enabled" graphic spec from t r to t r_ecc ? updated boot block operation to include dual-plane restrictions ? added t rcbsy spec to electrical specifications - program/erase characteristics ? added note for t prog and t prog_ecc specifications to electrical specifications - program/erase characteristics ? moved note from t rhw to t rhz in ac characteristics and operating conditions rev. a C 07/09 ? initial release; advance status 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. micron confidential and proprietary 4gb, 8gb, 16gb: x8, x16 nand flash memory revision history pdf: 09005aef83b25735 m60a_4gb_8gb_16gb_ecc_nand.pdf - rev. n 10/12 en 132 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.

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